ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs

Successive-approximation register analog-to-digital converters (SAR-ADC) are frequently the architecture of choice for medium-resolution applications. SAR products on the market can operate at maximum sample rates up to several megahertz. However, designers match their application needs with much slower SAR-ADCs in an effort to reduce cost and layout headaches. On the market, the SAR-ADC resolutions range from 8 to 18 bits.

This style of device has a small form factor and provides low-power consumption, which is critical for battery-powered applications. In this article, we examine the inner workings of the SAR-ADC and the converter’s driver requirements.

How the SAR-ADC works

The SAR-ADC (Figure 1) captures an analog voltage signal, converts that signal to a digital word. The analog signal is captured with either an external sample/hold device or the SAR-ADC’s internal sample/hold function. The SAR-ADC compares this input voltage to known fractions of the converter’s external or internal voltage reference (VREF). This reference sets the full-scale input voltage range of the converter. Modern SAR-ADCs use a capacitive, digital-to-analog converter (C-DAC) to successively compare bit combinations and set or clear appropriate bits into a data register.

Click on image to enlarge.

Figure 1. This is a model of the internal sampling mechanism for a modern SAR-ADC 16-bit converter. After acquiring the signal at VS, the chip select transitions from high to low and opens the input switch (S1).

At the input of a SAR converter, the input signal first sees a switch. Notice, that a closed switch creates a switch resistance (RIN) in series with a capacitive array. The top side of these capacitors connects to the inverting input of a comparator. The bottom side can tie into the input voltage, the voltage reference (VREF), or ground (V–). Initially, the bottom side connects to the input signal, VS. Once the capacitive array completely acquires the input signal, the input switch (S1) opens and the converter starts the conversion process.

During the conversion process, the bottom side of the MSB capacitor connects to VREF while the other capacitors connect to V– (or system ground). This action redistributes charge among all the capacitors. The comparator’s inverting input moves up or down in voltage according to charge balancing. If the voltage at SC is greater than half VREF, the converter assigns “0” to the MSB and transmits that value out of the serial port. If this voltage is less than half VREF, the converter transmits a “1” out of the serial port, and the converter connects the MSB capacitor to V–. Following the MSB assignment, this process repeats with the MSB-1 capacitor. Note that Figure 1 does not show the MSB-1 capacitor, but its value is 8C.

The time required for the SAR-ADC conversion process to occur consists of the acquisition and convert time. At the conclusion of the total conversion process, the SAR-ADC goes into a sleep mode.

Driving your SAR-ADC

The optimized ADC driver circuit in Figure 2 uses an operational amplifier (op amp) to separate the SAR-ADC from high impedance input source, VSIG. The following R/C low-pass circuit (RISO and CISO) performs functions going back to the op amp and forward to the SAR-ADC. RISO keeps the amplifier stable by isolating the amplifier’s output stage from CISO. CISO provides a nearly perfect and stable input source to the SAR-ADC. This CISO tracks the voltage’s input signal and provides the appropriate SAR-ADC charge during the converter’s acquisition time.

Click on image to enlarge.

Figure 2. The SAR-ADC application design requires a driver circuit (op amp, RISO, and CISO) to ensure that the ADC has a stable input signal during the converter’s acquisition period.

As you design your SAR-ADC circuit, first determine what your input signal looks like in terms of the bandwidth and full-scale range. Then, your selected SAR-ADC should match the bandwidth of the input signal per nyquist. This converter should also have the appropriate resolution for your system. In this design, the critical SAR-ADC specifications are the cumulative value of the capacitive array, CIN (which is equivalent to the SAR-ADC’s input capacitance), the converters full-scale input range, and the acquisition time (tAQU).

Now we move on to defining RISO and CISO by determining their values. The Figure 3 scope capture shows the input charge-injection transients of a SAR-ADC (ADS8326). In this measurement, there is a 10 kOhm resistor between the amplifier buffer and the SAR-ADC (Ch1). The start-conversion or chip select signal appears on the top curve (Ch4). Be aware that the input impedance presented to a SAR converter should never be as high as 10 kOhm? but this allows us to see the high-frequency current spikes at this SAR-ADC’s input.

Click on image to enlarge.

Figure 3. A 10 kOhm resistor captures the magnitude of the charge injection at the input of the 16-bit SAR-ADC (Ch1). The CS pin initiates each occurrence of spur, which occurs during the ADC’s acquisition period (Ch4).

The charge injection at the input of the SAR-ADC occurs as the converter is acquiring the input signal. These high-frequency spikes present a very demanding load to the driving op amp.

As illustrated in Figure 1 , the SAR converter rarely has a built-in input buffer amplifier. This circuit requires an op amp with a distortion free, rail-to-rail, input stage (see OPA364 data sheet, pg 8). The output stage of this amplifier spans from 100 mV to 100 mV below the positive supply.

The functions of RISO and CISO (Figure 2 ) is to provide a path for this charge injection to ground and to isolate the op amp output from these transients. RISO and CISO effectively accomplish their tasks of isolating the amplifier from the capacitive load and absorbing charge spikes from the SAR-ADC. However, these two components also modify the amplifier’s open-loop gain response as can be seen in a bode plot.

Figure 4 shows an example op amp, bode plot for this system. See how the left y-axis plots the open-loop and closed-loop gain of our amplifier. The right y-axis plots the open-loop phase response of the amplifier. The x-axis plots the frequency.

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Figure 4.  OPA364 open-loop gain/phase vs frequency with an RISO|CISO load.

The open-loop gain curve for this amplifier (OPA364) has a gain of 100 dB at 10 Hz. As frequency increases, this gain curve changes (~100 Hz) to a –20 dB/decade slope. This slope continues until the curve continues past 0 dB. The frequency at the intersection point between the open loop gain curve and 0 dB is 7 MHz.

When the external circuit (RISO|CISO) loads the amplifier, the open-loop gain curve is modified. In Figure 4, the blue curve represents the modified open loop curve. RISO and CISO, along with the output resistance of the amplifier, generate a pole at fPX and a zero at fZX. As shown in Figure 4 , the pole from RISO and CISO occurs at 769 kHz and the zero occurs at 1.6 MHz. The slope of this modified open-loop gain curve changes from –20 dB/decade to –40 dB/decade slope with fPX and reverts back to a slope of –20 dB/decade with the zero, fPZ at 1.6 MHz.

Circuit stability is defined at the intersection point (3.2 MHz) of the open-loop gain curve and the closed-loop gain curve. At this intersection point, if the difference between the slopes of these two curves is 20 dB/decade, the amplifier will be stable. If the difference between these slopes is greater than 20 dB/decade (for example, 40 dB/decade) the amplifier circuit will be marginally stable.

To minimize the effects of nonlinearities in the internal sampling capacitor, as well as minimize the charge injection’s effect on the input voltage, the minimum CISO value is twenty times the size of the internal SAR-ADC sampling capacitor. One finds the RISO value by noting that this R|C circuit must fully settle within the acquisition time of the converter.

This is a quick overview of the SAR-ADC input structure and the design strategy for the analog driving stage. The SAR-ADC’s input structure is equal to the sampling capacitive array during the converter’s acquisition time. To ensure that the input signal remains stable during the acquisition time, an effective design strategy places an R|C pair between the output of the amplifier and input of the converter. If you are curious about the calculation details for this R/C design, refer to References 1 and 2.   

Next month you will see Part 4 of this series . Part 4 will contrast the operation of the SAR-ADC with the delta-sigma converter.


1.    “External components improve SAR-ADC accuracy,” Baker, Oljaca, EDN, June 7, 2007.
2.    “Start with the right op amp when driving SAR ADCs,” Oljaca, Baker, EDN, Oct 16, 2008.   
3.    Download these datasheets: OPA364, ADS8361.

About the Author

Bonnie Baker is a Senior Applications Engineer with the Webench team for Texas Instruments and has been involved with analog and digital designs and systems for over 25 years. She has written hundreds of articles, design and application notes, conference papers, and authored a book: “A Baker’s Dozen: Real Analog Solutions for Digital Designers.” Bonnie can be reached at 

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