The delta-sigma ADC tackles the application demands of a slow analog signal that requires a high signal-to-noise-ratio (SNR) and wide dynamic range. But, the delta-sigma converter is not the only device that tackles these application requirements. You will find that designers also utilize SAR-ADCs in these lower frequency applications.

The SAR-ADC system usually requires an analog gain stage and a complete anti-aliasing filter, where the delta-sigma converter does not require these external functions. The delta-sigma converter has much of the required signal conditioning functions designed within the chip and performs these functions in the digital domain. As a matter of fact, the delta-sigma ADC can nearly be considered as a system-on-a-chip (SoC).

In this article, we investigate the position of the delta-sigma converter in the signal chain circuit, the overall operation of the delta-sigma converter, the delta-sigma noise shaping phenomena, and the utilization of process gain within the delta-sigma converter. Although this article does not provide a comprehensive treatment of the delta-sigma converter, we use these concepts as we compare the SAR-ADC and delta-sigma converter at the system level.

**Delta-sigma ADC signal chain**

The signal chain for the delta-sigma converter application starts with the sensor (**left side of Figure 1** ). Contrary to a typical SAR-ADC system, there are no analog gain circuits, such as an amplifier and instrumentation amplifier, following the sensor block. Between the sensor and the delta-sigma converter, there is an anti-aliasing, low-pass filter. The delta-sigma converter and the SAR-ADC anti-aliasing filter designs are significantly different. With a SAR converter, the anti-aliasing filter usually has an active fourth to eighth order implementation, requiring two to four amplifiers. As **Figure 1** shows, the delta-sigma anti-aliasing implementation generally requires only a first order, passive filter ** _{[1]} ** .

**Click on image to enlarge.****Figure 1. Typical delta-sigma converter signal path includes the signal source element and an anti-aliasing filter.**

Circuit designers find the simplicity of this signal chain attractive. The required external elements are the passive, anti-aliasing components and the voltage reference.

**Delta-sigma internal modules**

The core of the delta-sigma converter has an analog modulator, followed by a digital / decimation filter **(Figure 2** ). For most kinds of ADCs, the data rate and sampling rate are the same; each input sample converts to one output code. In contrast, the delta-sigma, acquires many input samples to produce one output code. This delta-sigma sampling algorithm lengthens the acquisition time.

**Click on image to enlarge.**

**Figure 2. The principal core of all delta-sigma converters contains a modulator and digital filter.**

While most converters have only one sample rate, the delta-sigma converter actually has two: the input sampling rate, Fs (based on the modulator clock); and the output data rate, Fd (a fraction of the modulator clock). The Fd value is the corner frequency of the internal digital/decimator filter. One uses Fd to define the corner frequency of delta-sigma converter’s external anti-aliasing filter.

In Figure 2, the delta-sigma’s modulator samples and quantizes the input signal in a coarse fashion, by producing a one-bit stream of data at a very high rate ** _{[2]} ** . Unlike most quantizers, the delta-sigma modulator includes an integrator, which has the effect of shaping the quantization noise.

**Noise shaping and using the decimation ratio**

The output of the modulator in the time domain signal looks uneventful. Averaging this signal produces the value of the input signal. The frequency domain representation shows a different story. In the frequency domain, the accumulated modulator output data creates the input signal, with most of the noise shaped into frequencies above the input signal frequency.

The following digital / decimator (low-pass) filter preserves the input signal as well as attenuates this higher frequency noise. It also takes this sampled modulator data and converts it into a precise digital signal _{[3].}

Many delta-sigma converters have a programmable data rate. The decimation ratio (DR) of a delta-sigma converter equals the number modulator samples per data output, or DR = Fs/Fd. Decimation ratio values range anywhere from four or eight (ADS1605) to 32,768 (ADS1256). The relationship between the output data rate and the sampling rate directly impacts the effective-number-of-bits (ENOB) at the converter’s output.

Consider the output spectrum of a delta-sigma modulator (Fs) versus the digital / decimation filter (Fd) in **Figure 3** . The modulator sample rate (Fs) shapes the quantization bandwidth. The data rate (Fd) is always smaller than Fs, as in **Figure 3A and 3B** . The signals from zero to Fd are included in the converter’s output. Note the noise level in this frequency band. The ENOB describes noise and distortion in the converter’s output data. The ENOB in Figure **3A** is higher than the ENOB in Figure **3B** ** _{[4]} ** .

**Click on image to enlarge.****Figure 3. The digital / decimation filter cut-off frequency (Fd) is lower than the modulator’s sampling frequency (Fs). The modulator’s integrator successfully shapes quantization noise toward Fs.**

**Using digital process gain**

Implementation of the SAR-ADC external, analog-gain stage typically includes at least one, if not more, operational amplifiers. Designers use these amplifiers to gain and level-shift the analog signal. The delta-sigma converter handles these analog functions with an internal digital process gain. You can use the delta-sigma’s process gain to create a 10-, 12-, or 16-bit system with a 24-bit converter. This eliminates the external gain and level shift circuits ** _{[5]} ** .

For instance, a noiseless 24-bit delta-sigma converter has 4096 individual, 12-bit converters across the converter’s output range. Noiseless, 24-bit delta-sigma converters are hard to find, but a delta-sigma converter with an effective resolution of 19.5-bits (rms) is more realistic. **Figure 4** shows the relationship between output codes and noisy bits of this realistic 24-bit delta-sigma converter.

**Click on image to enlarge.****Figure 4. Capturing the right output codes of the 19.5-bit (rms) delta-sigma converter**

can provide a level shift and process gain.

can provide a level shift and process gain.

**Figure 4** diagrams the technique used to absorb the analog functions of gain and level-shift into the delta-sigma converter. Ignoring the most-significant-bits allows you to implement a level-shift function. Process gain is equivalent to an analog gain by determining the location of the new MSB at the converter’s output. A gain change is implemented by shifting the 12-bit window in **Figure 4** to the right or towards the converter’s least significant bit (LSB). Each one-bit shift to the right is equivalent to doubling the process gain. As in the analog domain, an increase in process gain lessens the input range. In **Figure 4** , you can increase the process gain to 64 or 128. This is equivalent to an analog gain of 64 V/V or 128 V/V.

With this technique, you have the full resolution of 224 codes at our disposal. Select the ADC range portion and focus just on the area where the signal response is occurring. Note that you are trading off the loss of your 24-bit converter’s dynamic range with the elimination of the external analog circuitry.

**Conclusion**

Delta-sigma converters are available with many additional features that make them ideal for data acquisition. Many of these types of converters include a programmable-gain amplifier (PGA) and input buffer that can further reduce the requirements for external signal conditioning. Some also have special features for sensor connections, like burnout current sources.

Delta-sigma converter applications have fewer components as compared to SAR-ADC circuits. While in operation, the delta-sigma ADC continuously oversamples an input voltage signal. The ADC then applies a digital filter on these samples to achieve a multi-bit, low-noise digital output. The byproduct of this algorithm is a higher dynamic range and lower output speeds. Many designers focus on the number of output bits that this type of converter can produce. However, the often overlooked hidden feature is process gain. This feature allows the designer to eliminate external analog circuitry in these low-frequency signal chains.

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**References**

**1.** “Delta-sigma antialiasing filter with a mode rejection circuit,” Bonnie Baker, EDN, September 17, 2012.

**2.** “Delta-sigma ADCs in a nutshell, part 2: the modulator,” Bonnie Baker, EDN, January 24, 2008.

**3.** “Delta-sigma ADCs in a nutshell, part 3: the digital/decimator filter,” Bonnie Baker, EDN, February 21, 2008.

**4.** “A glossary of analog-to-digital specifications and performancecharacteristics,” Bonnie Baker, Application Report (SBAA147B), Texas Instruments, October 2011.

**5.** “Take a risk; throw away those bits!,” Bonnie Baker, EDN, October 22, 2009.

**Related articles**

ADC Basics (Part 1): Does your ADC work in the real world?

ADC Basics, (Part 2): SAR and delta-sigma ADC signal path

ADC Basics (Part 3): Using successive-approximation register ADC in designs

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