# ADC Basics, Part 7: Key Op Amp Frequency & Timing Specifications

We are nearing the discussion about selecting the total signal path to the ADC, but first we have a little more homework to do. Let’s talk about amplifier bandwidth, settling time, and clock rates of programmable gain amplifiers (PGAs) and multiplexers.

We are building a single-supply, 12-bit, SAR-ADC system for a multiplexed circuit, handheld meter, data logger, automotive, or other monitoring systems. We've already looked at the various ADC topologies and fundamental DC and noise characteristics that impact our systems. (See: ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs; ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design; and ADC Basics, Part 5: Key ADC Specifications for System Analysis.) Figure 1 shows our fundamental system.

Figure 1

Typical signal chain path for circuits using SAR-ADCs.

In the previous article in this series (ADC Basics, Part 6: Key Op-Amp DC & AC Specifications), we discussed the voltage-feedback and operational amplifier (op amp) specifications that impact the ADC’s DC input range. In this article, we use the following list to look at the major frequency components that affect our system:

• Bandwidth
• Settling time
• PGA and multiplexer clock rates

Bandwidth
Circuit gain and the signal of interest dictate the amplifiers’ bandwidth. Figure 2 shows the influence of these issues.

Figure 2

Voltage-feedback amplifier gain and phase response with a unity-gain bandwidth of ~50MHz and closed-loop gain of 16V/V or ~24dB.

It is tempting to match the amplifier’s unity-gain-bandwidth (UGBW) to the input signal’s bandwidth. There are two reasons this will not work: 1) the amplifier gain versus frequency response; and 2) the signal’s full-scale signal.

For the first, you can look at the open-loop curve in Figure 2. Here the amplifier’s open-loop gain falls at a rate of 20dB/decade from ~50Hz to ~50MHz. From this graph, you can quickly see that the closed-loop bandwidth in your system will be approximately 2 MHz, instead of the UGBW of ~50 MHz.

The full-scale signal is the second reason you would not design around the amplifier’s UGBW. The amplifier’s slew-rate (SR) dictates the amplifier’s full-scale-bandwidth (fFSBW ). To calculate: fFSBW = SR/(π•Vp-p), where Vp-p is your signal’s peak-to-peak value.

If you deal with both of these issues, you will make your first step towards determining the real bandwidth of your amplifier system and, consequently, be able to choose appropriate amplifiers.

Settling time
All analog ICs in the signal path require time to settle within the error band of the ADC’s one-half LSB. For instance, if there is a 12-bit converter in the signal path, the analog signal must settle within a 0.01% error band (± ΔE0 ) or 100%•(1/2(N+1) ), where N is the number of bits.

An amplifier’s settling-time is from when the step-input is applied to the time where the amplifier output enters and remains within a specified error band, ±ΔE0 (Figure 3). Settling-time includes a propagation delay, plus the time required for the output to slew, recover from the overload condition associated with slew, and settle to within the specified ±ΔE0 .

In Figure 3, you can see the basic regions of an amplifier’s step-response are propagation delay, slew, recovery, and linear settling. In this figure, the desired final value is within the acceptable error band of ±ΔE0 .

Figure 3

Given a step response at the input, this diagram explains the amplifier’s settling time.

As you can imagine, an amplifier’s 0.01% settling time is longer than the same amplifier’s 0.1% settling time. Figure 4 illustrates this very clearly. Here the test engineer measured the amplifier’s settling time in a negative gain.

Figure 4

The settling time error band is dependent on the acceptable percentage of error.

The required analog settling time for a 16-bit converter is approximately 0.001%. You might ask why we are discussing 16-bit converters for our 12-bit system. The answer can be found in ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design. If we use a 16-bit converter for our 12-bit system, it is highly likely that we will be using process gain in combination with analog gain.

Clock rates of PGAs and multiplexers
Now let’s tackle the overall timing of your multiplexed circuit. The clock rates of the PGA and/or multiplexer in our system require special consideration. These rates will have a dramatic impact on the system’s conversion speed.

A primary characteristic of multiplexed systems is that they require fully settled conversions with zero latency. For instance, handheld meters require multiplexed systems that operate with a minimum amount of power with the intent of conserving battery power. On the other hand, with an automotive system, precision requirements are low. But there is a variety of sensors in the system that requires a multiplexer interface.

In Figure 5, the maximum clock rate to the PGA116 and ADS7886 is 10 MHz. Although the clock rate to the ADS7886 can be 20 MHz, the 10 MHz clock is applied to the converter in order to maintain consistency across the system.

If the step response signal occurs at the input of the PGA116’s internal amplifier (which is a good assumption in a multiplexed environment), the analog portion of this circuit requires 4.2 ms to reach a 0.01% level of accuracy. The ADS7886 requires 16 clocks, or 1.6 ms, to acquire and convert the input signal.

Figure 5

10MHz clock rates to the PGA and ADC, as well as the settling time of the analog amplifiers, encompass the total system conversion time.

The total system conversion time for the PGA116/ADS7886 combination is 7.4 ms or 135 ksps. In our investigation, we add a guard band of 30% to allow for integrated-chip variations in capacitance, resistance, transconductance (gm), variations over temperature, time, and production lots of the PGA116’s internal op amp. For instance, the internal PGA116 capacitances can change up to ±15%. Additionally, the op amp transistor’s gm can vary between ±5 and ±15%. Assuming a variation of unity gain bandwidth at 25°C with three times sigma, we can use ±30% as a good starting point. Using the guard band on the times listed above, 4.2 ms is allotted for the PGA116/OPA350 to settle.

Conclusion
Our background work is now complete! In the next five articles we will compare systems that all have a multiplexer, a gain cell, and a converter. In the five cases under consideration, these functions can appear in either the analog or digital domain, but all five systems are able to solve the defined application space requirements.

Next time we will look at our first system, which has a 10-channel, PGA (PGA116) teaming up with the 12-bit ADC (ADS7886). What do you think about the consequence of counting (or not counting) the impact of all of the analog timing issues. Tell us about experience!

References:

1. Bruce Trump, The Signal: Settling Time, Texas Instruments, June 11, 2013
2. PGA116 datasheet

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## 7 comments on “ADC Basics, Part 7: Key Op Amp Frequency & Timing Specifications”

1. Dirceu
July 11, 2013

Hello Bonnie,

could you explain the text “Open loop gain = 16” in Figure 2? I think that curve would be available from the manufacturer, right? 20 log (1258,925) = 122

2. Davidled
July 11, 2013

I am curious how designer selects either open loop gain or closed loop gain.  Voltage gain curve is slightly different between open loop gain and close loop gain in the frequency domain. Well, if my system frequency is more than 100 MHz (10 GHz), then other voltage-feedback amplifier gain chip might be used.

July 11, 2013

Dirceu – just a typo – someone was typing too quickly. All better now.

4. RedDerek
July 16, 2013

Identifying the settling time of the amplifier is crucial and I was curious as to what the settling time for some the amplifiers I use – granted I work in the low frequency area mostly. However, I never bothered to look for the t-s spec and went back to review the opamps I use. Definitely not for the 1Gs 12-bit capability I just researched – I would need 50+ amplifiers. So I gather that most digitizing scopes are 8-bit so that they do not need such high speed or high quantity of opamps.

5. Bonnie Baker
July 22, 2013

MASTER,

Actually the open loop gain of a voltage feedback amplifier is maily important in terms of bandwidth and DC gain. The open-loop gain of any voltage-feedback amplifier will change from part to part in terms of the acutal bandwidth and DC gain (by about +/- 30%). The closed loop gain is important in terms of how much gain. The difference between these two curves exist in the lower frequencies. The closed loop gain with an amplifier is more stable because the gain is dependant on the passive devices (such as resistors) that surrund the amplifier.

6. SunitaT
July 31, 2013

Perhaps the most significant characteristic for an ADC used in a communications application is its spurious-free dynamic range (SFDR). The SFDR specification is to ADCs what the third-order intercept specification is to mixers and LNAs. SFDR of an ADC is well-defined as the ratio of the rms signal amplitude to the rms value of the peak spurious spectral content. SFDR is usually plotted as a function of signal amplitude and might be expressed relative to the signal amplitude (dBc) or the ADC full-scale (dBFS).

7. Bonnie Baker
July 31, 2013

Sunita,

You are correct in this observation. SFDR is an important specificaiton if you are working in the communications environment. However, the emphasis of this article series is more towards the instrumentation areana. In this arena, the SAR ADC competes with the Delta-sigma ADC. The key ADC specifications for these types of applications are primarily linearity, offset, gain errors, and noise.

You are bringing up a good point. The next topic for this type of series should be centered on the communicaitons type circuits. Thanks for your inputs.

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