What do the circuits look like for 12-bit, analog-to-digital converter (ADC) systems? These systems can be found in handheld meters, data loggers, automotive systems, and monitoring systems, to name a few. If these circuits produce 4,096 possible digital outputs to the microcontroller or processor, what happens between the system input and output?
When accomplishing this level of digital output resolution, in the circuit it is possible to use a 12- or 16-bit SAR, or a 24-bit delta-sigma ADC. The systems we consider in this article and the next three (ADC Basics, Parts 9, 10, and 11) each have a multiplexer, gain cell, and converter. In the four cases we will consider, these functions can appear in the analog or digital domain. Regardless, all four systems are able to solve the defined application space requirements. The power to all systems is a single, 5V supply voltage. Each system is capable of producing gain changes from 1 to 128, and each system has an input multiplexer.
A four-system matrix
In our first system, a 10-channel, programmable gain amplifier (PGA) teams up with a discrete multiplexer and a 12-bit SAR-ADC. For this circuit, the PGA provides analog gains from 1 to 128. In our second system, we will use a multiplexed 12-bit SAR-ADC that allows the insertion of a PGA between its multiplexer and ADC function. Once again, the circuit's programmable-gain-amplifier provides analog gains from 1 to 128. Our third system uses the same programmable gain amplifier with a 16-bit SAR-ADC. This SAR-ADC provides a digital gain up to 16, and the PGA provides analog gains from 1 to 128. We will only be using the lower gains of 1, 2, and 4. The fourth system uses a 24-bit delta-sigma data converter to provide the multiplexing capability and system process gain within one chip.
In our discussion, we will establish system boundaries in order to facilitate our ability to make an “apples-to-apples” comparison between each system. All systems will have a 5V power supply. The programmable gain range is 1 to 128V/V. Given this range, all circuits will have a gain of 16.
PGA and a 12-bit SAR
Figure 1 shows the circuit in System 1. This circuit consists of a PGA followed by an ADC driver amplifier. The key PGA characteristics are low noise across its entire gain range and a quick throughput rate. The driver amplifier and resistor/capacitor (R/C) pair provide ample charge to the 12-bit ADC.
The PGA in Figure 1 has a 10-input multiplexed channels, a rail-to-rail input/output, and an input offset of 100μV (max). The PGA binary gains are 1, 2, 4, 8, 16, 32, 64, and 128. In our analysis, the PGA's configuration is 16V/V.
The PGA's low-noise performance is 22nV/√Hz @ 10kHz. The calculated value of the PGA noise, referred to as output (RTO), is equal to the PGA noise density at 10kHz (12nV/√Hz) times the square-root of the PGA closed-loop bandwidth times √(π/2). Next multiply this entire number by the PGA gain. The multiple of √(π/2) accounts for the noise in the frequency region beyond the PGA bandwidth (Equation 1).
The combined noise of the PGA and ADC is equal to 0.589μV (rms), which is less than 1 LSB (1.22mV). This is calculated using a root-sum-square in Equation 2:
The equivalent 12-bit accuracy of this system is equal to 0.597 least significant bit (LSB). You calculate this using Equation 3:
Figure 2 shows the timing characteristics of this circuit. The analog bandwidth of the PGA in a gain of 16V/V is equivalent to 1.6MHz (typ). This bandwidth creates a 0.01% settling time of 2.6μs. The gain-switching time of the PGA is 200ns. If you combine this settling time with the channel/gain-select time, you will see that the device needs 3.0μs (typ) to settle from a step response at the input of the internal amplifier.
The unity gain bandwidth of the operational amplifier (op amp) in Figure 1 is 38MHz. The settling time (1.3μs) of this amplifier in a gain of one is low enough so that the PGA dominates.
In our investigation, we added a guard-band of 30 percent to allow for integrated chip (IC) production variations with IC capacitance, resistance, transconductance (gm ) variations over temperature, time, and production lots of the PGA's internal op amp.
The total system settling time equals Equation 4:
Although the clock rate to the 12-bit ADC can be up to 20MHz, we use a 10MHz clock while maintaining consistency across the system. The PGA gain and channel programming time requires 16 clocks (1.6μs). After the PGA changes channels, the analog output settles in at 4.2μs. The ADC requires 16 clocks (1.6μs) to acquire and convert the input signal.
Combining the PGA programming and settling time and ADC throughput time creates a system data rate of 135ksps.
The PGA power specification for a 5V supply is 5.4mW (typ). The power specification for the op amp we chose (OPA350) is 26mW with no shutdown capability. The ADC power dissipation is 7.5mW. Consequently, there is little advantage to putting this circuit into shutdown mode, unless the power to the op amp is turned off.
Finishing with perhaps the most important specification is the price of this system. The price of $4.85 excludes the cost of discrete components, power supply, voltage reference, and board real-estate plus fabrication.
If we look at this system across the gain range of the PGA, in this circuit we find that the PGA dominates the noise contribution portion. Near a gain of 16V/V, this PGA/ADC combination provides excellent accuracy at about 0.006%. Once the PGA exceeds ~ 125V/V, this system no longer matches the 12-bit accuracy criteria.
Referring to Table 1, this system produces 11.97 effective bits, which is effectively 4011 output codes. The analog output swing is somewhat limited, but not enough to impact the amplifier and ADC offset and gain errors.
This system has a very low-cost factor, reasonable power-down capability, and excellent noise performance.
How would you expect this system to rank against the other three systems that we are going to evaluate? Remember that our second system uses a multiplexed 12-bit SAR-ADC that allows the insertion of a PGA between its multiplexer and ADC function. Our third system combines the programmable-gain-amplifier with a 16-bit SAR-ADC. Our fourth system uses a delta-sigma converter.
For more information, download these datasheets:
- ADC Basics, Part 1: Does Your ADC Work in the Real World?
- ADC Basics, Part 2: SAR & Delta-Sigma ADC Signal Path
- ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs
- ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design
- ADC Basics, Part 5: Key ADC Specifications for System Analysis
- ADC Basics, Part 6: Key Op-Amp DC & AC Specifications
- ADC Basics, Part 7: Key Op Amp Frequency & Timing Specifications