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ADC Basics, Part 8: A 4-System Matrix With PGA + 12-bit SAR

What do the circuits look like for 12-bit, analog-to-digital converter (ADC) systems? These systems can be found in handheld meters, data loggers, automotive systems, and monitoring systems, to name a few. If these circuits produce 4,096 possible digital outputs to the microcontroller or processor, what happens between the system input and output?

When accomplishing this level of digital output resolution, in the circuit it is possible to use a 12- or 16-bit SAR, or a 24-bit delta-sigma ADC. The systems we consider in this article and the next three (ADC Basics, Parts 9, 10, and 11) each have a multiplexer, gain cell, and converter. In the four cases we will consider, these functions can appear in the analog or digital domain. Regardless, all four systems are able to solve the defined application space requirements. The power to all systems is a single, 5V supply voltage. Each system is capable of producing gain changes from 1 to 128, and each system has an input multiplexer.

A four-system matrix
In our first system, a 10-channel, programmable gain amplifier (PGA) teams up with a discrete multiplexer and a 12-bit SAR-ADC. For this circuit, the PGA provides analog gains from 1 to 128. In our second system, we will use a multiplexed 12-bit SAR-ADC that allows the insertion of a PGA between its multiplexer and ADC function. Once again, the circuit's programmable-gain-amplifier provides analog gains from 1 to 128. Our third system uses the same programmable gain amplifier with a 16-bit SAR-ADC. This SAR-ADC provides a digital gain up to 16, and the PGA provides analog gains from 1 to 128. We will only be using the lower gains of 1, 2, and 4. The fourth system uses a 24-bit delta-sigma data converter to provide the multiplexing capability and system process gain within one chip.

In our discussion, we will establish system boundaries in order to facilitate our ability to make an “apples-to-apples” comparison between each system. All systems will have a 5V power supply. The programmable gain range is 1 to 128V/V. Given this range, all circuits will have a gain of 16.

PGA and a 12-bit SAR
Figure 1 shows the circuit in System 1. This circuit consists of a PGA followed by an ADC driver amplifier. The key PGA characteristics are low noise across its entire gain range and a quick throughput rate. The driver amplifier and resistor/capacitor (R/C) pair provide ample charge to the 12-bit ADC.

Figure 1. PGA followed by an operational amplifier that drives a 12-bit ADC

Figure 1. PGA followed by an operational amplifier that drives a 12-bit ADC

The PGA in Figure 1 has a 10-input multiplexed channels, a rail-to-rail input/output, and an input offset of 100μV (max). The PGA binary gains are 1, 2, 4, 8, 16, 32, 64, and 128. In our analysis, the PGA's configuration is 16V/V.

Noise
The PGA's low-noise performance is 22nV/√Hz @ 10kHz. The calculated value of the PGA noise, referred to as output (RTO), is equal to the PGA noise density at 10kHz (12nV/√Hz) times the square-root of the PGA closed-loop bandwidth times √(π/2). Next multiply this entire number by the PGA gain. The multiple of √(π/2) accounts for the noise in the frequency region beyond the PGA bandwidth (Equation 1).

The combined noise of the PGA and ADC is equal to 0.589μV (rms), which is less than 1 LSB (1.22mV). This is calculated using a root-sum-square in Equation 2:

The equivalent 12-bit accuracy of this system is equal to 0.597 least significant bit (LSB). You calculate this using Equation 3:

System timing
Figure 2 shows the timing characteristics of this circuit. The analog bandwidth of the PGA in a gain of 16V/V is equivalent to 1.6MHz (typ). This bandwidth creates a 0.01% settling time of 2.6μs. The gain-switching time of the PGA is 200ns. If you combine this settling time with the channel/gain-select time, you will see that the device needs 3.0μs (typ) to settle from a step response at the input of the internal amplifier.

Figure 2. Timing diagram for PGA and the 12-bit ADC from Figure 1

Figure 2. Timing diagram for PGA and the 12-bit ADC from Figure 1

The unity gain bandwidth of the operational amplifier (op amp) in Figure 1 is 38MHz. The settling time (1.3μs) of this amplifier in a gain of one is low enough so that the PGA dominates.

In our investigation, we added a guard-band of 30 percent to allow for integrated chip (IC) production variations with IC capacitance, resistance, transconductance (gm ) variations over temperature, time, and production lots of the PGA's internal op amp.

The total system settling time equals Equation 4:

Although the clock rate to the 12-bit ADC can be up to 20MHz, we use a 10MHz clock while maintaining consistency across the system. The PGA gain and channel programming time requires 16 clocks (1.6μs). After the PGA changes channels, the analog output settles in at 4.2μs. The ADC requires 16 clocks (1.6μs) to acquire and convert the input signal.

Combining the PGA programming and settling time and ADC throughput time creates a system data rate of 135ksps.

Power
The PGA power specification for a 5V supply is 5.4mW (typ). The power specification for the op amp we chose (OPA350) is 26mW with no shutdown capability. The ADC power dissipation is 7.5mW. Consequently, there is little advantage to putting this circuit into shutdown mode, unless the power to the op amp is turned off.

Finishing with perhaps the most important specification is the price of this system. The price of $4.85 excludes the cost of discrete components, power supply, voltage reference, and board real-estate plus fabrication.

Conclusion
If we look at this system across the gain range of the PGA, in this circuit we find that the PGA dominates the noise contribution portion. Near a gain of 16V/V, this PGA/ADC combination provides excellent accuracy at about 0.006%. Once the PGA exceeds ~ 125V/V, this system no longer matches the 12-bit accuracy criteria.

Figure 3. Equivalent bits vs. PGA gain

Figure 3. Equivalent bits vs. PGA gain

Referring to Table 1, this system produces 11.97 effective bits, which is effectively 4011 output codes. The analog output swing is somewhat limited, but not enough to impact the amplifier and ADC offset and gain errors.

Table 1. System specifications for the circuit in Figure 1

Table 1. System specifications for the circuit in Figure 1

This system has a very low-cost factor, reasonable power-down capability, and excellent noise performance.

How would you expect this system to rank against the other three systems that we are going to evaluate? Remember that our second system uses a multiplexed 12-bit SAR-ADC that allows the insertion of a PGA between its multiplexer and ADC function. Our third system combines the programmable-gain-amplifier with a 16-bit SAR-ADC. Our fourth system uses a delta-sigma converter.

References:
For more information, download these datasheets:

Related posts:

24 comments on “ADC Basics, Part 8: A 4-System Matrix With PGA + 12-bit SAR

  1. samicksha
    September 10, 2013

    This is mind bogling i revised this blog 3 times to understand and considering ADC works by sampling the value of the input at discrete intervals in time…

  2. Bonnie Baker
    September 10, 2013

    Samicksha,

    Yes, the ADC does sample the input value at discrete intervals in time. But let's go back. The input signals are in the analog (continuous) domain. These signals travel to the front of the PGA multiplexer and at that time we start to separate these signals into “packets”. These time packets are defined by the PGA and its ability to change the multiplexer configuration, which allows one signal or channel to pass through. After the channel selection is made, the signal at the PGA output needs time to settle. You could perceive this as another time delay before the conversion, but I personally take the system view in that the input signal through the conversion process to the output requires 7.4 us to complete. So the allowable maximum analog bandwidth in this system is 135 kHz / 2 = 67.5 kHz. By the way, make sure you have adequate anti-aliasing filtering on each channel.

  3. samicksha
    September 11, 2013

    Thanx Bonnie, but i guess if we talk about PGA, gain can be controlled by external digital or analog signals.

  4. Bonnie Baker
    September 11, 2013

    Samicksha,

    The PGA is actually controlled with the microcontroller or processor. Thankfully, this is a digital activity that is dynamic as opposed to the analog hardwire technique.

  5. BobMcK
    September 12, 2013

    Hi Bonnie.

    I have a quick question about the noise free resolution of the ADC. If  we assume the noise is normally distributed (AWGN), then rms noise voltage of 729uVrms is equal to the standard deviation of the noise probability density function. 99.9% of the time, the noise will be within +/- 3.3 standard deviations of the mean, giving a pkpk noise voltage of 6.6*729uVrms = 4.8114mVpkpk. This equates to (4.8114mV/5V)*2^12 = 3.941-noise-counts. I convert counts to bits by taking the log2, giving log2(3.941) = 1.979-noise-bits. The guaranteed noise free resolution of the ADC is then (12-bits – 1.979-noise-bits) = 10.021-noise-free-bits.

    This does not tie up with your calculation that the ADC is accurate to 0.597-bits, giving a noise free resolution of 11.403-bits.

    Can you please help me see whereI have gone wrong?

    Thank you in advance for your help.

  6. Juergen1
    September 12, 2013

    Hi Bonnie,

     

    thanks for the great article.

    I have two questions more or less related to your article.

    – When does a SAR ADC need a driver amplifier in general, like the OPA350 in your article? How can I exactly determine if a SAR ADC needs a driver amplifier ?

    – I have red your previous appl bulletins about ACF2101 switched integrator/transimp. amplifier.

    In our application we will use ACF2101 or IVC102. Can you make a comparison between them, apart from the fact that ACF2101 has two units inside? Which one is “better” from spec point of view?  Can I directly connect onyone of these to SAR without driver amplifier, as is shown in the data sheets?

     

    Thanks in advance.

    Tarik

     

  7. Bonnie Baker
    September 12, 2013

    Tarik,

    1.)   If the driving circuitry that you have is unable to handle the charge spikes that the converter creates at the beginning of conversion you will need the driver amplifier. You can determine that you have a problem by examining the quality of your output code. Try running an FFT on a sine wave input. Generally, I just insert an amplifier because I am aware that most amplifiers are not able to handle such a task. I am starting to write about this issue in my new TI blog; On Board With Bonnie . This should start to appear in the next week. It is important that you insure that the driver amplifier is stable because you are loading the output with a fairly large capacitor. This capacitor should be grater that 20 times the size of the input capacitance of the converter.

    2.)   The intent of the IVC102 was to design a single channel ACF2101. During the silicon development, the designer of the IVC102 designed in a little lower noise into the chip than the ACF2101. There were other specifications that were improved during this process. Both have the same bandwidth and slew rate specifications. In terms of connecting this device to a SAR converter, the amplifier of the IVC102 is able to drive a capacitive load up to 500 pF. This is definitely ample for any SAR converter as their input capacitance ranges from 20 to 50 pF, however there is the problem of the amplifier being about to quickly supply the needed change to the converter. I know that the data sheet suggests that you connect directly to the ADC, however you should test to make sure that your set up is not compromising the accuracy of you final conversion.

  8. Bonnie Baker
    September 12, 2013

    BobMcK,

    Your calculations are 100% correct. You have not gone wrong with your thinking. In your calculations, you are using a crest factor (CF) of 3.3. By the way, 3.3 was an industry standard that was settled on in the 1980s. In this article, I was very careful to not use the term “noise-free” because of the various definitions.

    With the term “noise free”, you are actually looking for noise occurrences outside a band of interest. If you use a CF of 3.3, the percentage of occurrences inside your limits are 99.9%. This would work for to a 3 digit display. If you use a CF of 4.9, the percentage of occurrences inside your limits are 99.999%. This would work for to a 5 digit display.

    As your calculations indicate, if this criteria is applied the number of bits is reduced from 11.403-bits to 10.021-bits.

  9. Juergen1
    September 13, 2013

    Thanks for the quick response Bonnie!

  10. BobMcK
    September 13, 2013

    Thanks for clearing that up for me Bonnie

  11. etnapowers
    September 13, 2013

    Bonnie, nice blog, I'd like to know if the 10 input signals have to satisfy any requirement in terms of bandwidth, frequence for a good A/D conversion.

  12. Bonnie Baker
    September 13, 2013

    Etnapowers,

    Very nice question. Each input can have a theoretical bandwidth of 67.5 kHz (1/2 nyquist), however as you cycle through the 10 channel multiplexer you can see that every channel will be visited every 74 us (7.4 us x # channels). If you use all 10 channels, the actual input frequency band would be 6.75 kHz (1/2 nyquist divided by # channels).  In both cases, the converter will provide good conversions as long as you remain under the above timing requirements. Considering these two extremes, I have put together systems where there are numerous conversions on one channel to read the characteristics of that channel (if I wanted to record heart beat details, for instance) and then move to the next channel to record events on the second channel. In this scenario, I am interested in status information not continuous information.

  13. etnapowers
    September 18, 2013

    Hi Bonnie, thank you for your exaustive answer. Do you think the bandwith of the opamps could also influence the overall bandwith of the system?

  14. Bonnie Baker
    September 18, 2013

     

    etnapowers,

    Your intuition is correct. Of course, the PGA bandwidth is important because it does service the signal transmission. The minimum bandwidth of this device with gain changes exceeds the overall throughput rate of the system. The OPA350 bandwidth is also critical. It must be appropriate when driving the SAR-ADC. The OPA350 bandwidth is 38 MHz. This far exceeds the system throughput time, however it is critical that the selection of this amplifier assists the SAR-ADC to convert an accurate 12-bits. The actual impact on the system throughput time is from the settling time of both of these devices.

  15. etnapowers
    November 18, 2013

    @Bonnie, thank you very much for your clarification.

    As I understand this the minimum bandwidth of the PGA is the bottom limit of the system bandwidth.

    Input signals having a bandwidth of 6.75 kHz are non vocal signals (that have  40 KHz bandwidth). To transmit a vocal signal only one of the inputs could be utilized for this system, is this correct?

     

     

  16. Bonnie Baker
    November 18, 2013

    Etnapowers,

    If you want to measure a vocal signal (<  40 kHz), the PGA116 is fully equipped to amplify that type of signal, independent of the programmed gain. The time limitation for this system is when you change the PGA gain and/or channel. This change requires 1.6 us. Additionally, when you make this type of change you need to allow 4.2 us (worst case) for the PGA signal to settle.

  17. Davidled
    November 18, 2013

    ->If you want to measure a vocal signal (<  40 kHz), the PGA116 is fully equipped to amplify that type of signal, independent of the programmed gain

    I wonder if there is a limitation for PGA 116 to measure data in the condition that vocal signal is greater than 40 kHz. I think that this would be related to sampling rate.

  18. Bonnie Baker
    November 18, 2013

    DaeJ,

    On the analog side, the PGA minimum full-scale frequency response (across all gains) is 100 kHz. You can tweak this to a higher frequency if you choose a PGA setting that allows this. There are some settling time issues, however in the audio band (assuming no step responses) this will have minimal impact.

     

    The maximum clock rate of the PGA is 10 MHz and the maximum clock rate of the ADC is 20 MHz. The PGA clock does limit this system, however if you keep the channel/gain of the PGA constant, you can convert the PGA signals with the ADC at a rate of 0.8 us or 1.25 MHz. Taking Nyquist into account the maximum rate would be at 625 kHz.

     

    This analysis suggests that this system will operate with a vocal signal greater than 100 kHz. This is good, because there are many audio-files that believe that we 'hear' or feel sounds well above the scientifically measured hearing range.

  19. etnapowers
    November 19, 2013

    “The time limitation for this system is when you change the PGA gain and/or channel”

     

    @Bonnie, could you cite some cases in which the change of the PGA gain or channel is required by the application? In case of failure or missed calibration of a channel for example?

     

  20. Bonnie Baker
    November 19, 2013

    Etnapowers,

    The simple answer to your question is that the PGA channel changes are obvious as the user is interested in the data from another channel. As you change the channel, it is possible that a new gain is required per the channel requirements.

    If you intend to use the PGA system calibration routine, you will need to configure CH0 appropriately and run the measurement algorithm described in the PGA116 data sheet. As you go through this calibration routine, the internal calibration channels need to be changed. After you select each calibration channel, the ADC must collect measurement data. Each calibration cycle (total two) requires a full 7.4 us to perform.

  21. etnapowers
    November 25, 2013

    Thank you Bonnie for explanation. I intended the calibration routine that, as per your description should take 2 x 7.4 us each time it is performed. This 14.8 us time interval could be a long time if the calibration is required many times and the data trasmission effective rate could be decreased accordingly.

  22. Bonnie Baker
    November 25, 2013

    Etnapowers,

    Your calculations are correct, but remember, you are calibrating the offset and gain error of the ADC, not the PGA. Re-calibration is not needed as you change the Mux or Gain of the PGA. You would want to recalibrate if there is a temperature change or at start-up.

  23. etnapowers
    November 25, 2013

    Hi Bonnie, thank you again for your informations.

    Does the temperature change rate play a role in the recalibration of the ADC ? Is there a threshold value?

     

  24. Bonnie Baker
    November 25, 2013

    Etnapowers,

    If you look at the ADS7886 specifications, typically there is a slight variation in gain error in temperatures below 15C. Typically, the offset error seems to be rock solid. This is true for this product, but if you choose to use another, please check the product data sheet for information.

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