We are looking for 12-bit systems that are appropriate for handheld meters, data loggers, automotive systems, or monitoring systems. These systems must produce 4,096 possible digital outputs to a microcontroller or processor. That is an easy task to achieve; however, there is more to the system than a simple 12-bit conversion. Each system has an input multiplexer and should be capable of producing gain changes from 1 to 128 V/V.
In ADC Basics, Part 8: A 4-System Matrix With PGA + 12-bit SAR, we looked at a system with an input multiplexer, followed by a programmable-gain-amplifier (PGA). The signal went into a 12-bit successive approximation analog-to-digital converter (SAR-ADC). This system worked well enough, but let's looks at a different design strategy.
In our second system, an 8-channel, 12-bit SAR-ADC allows for the inclusion of an analog function between the multiplexer and ADC. Embedded in this space is a single-channel PGA and an ADC op amp (Figure 1). Once again, the power supply in this system is 5V. The system programmable gain range is 1 to 128.
PGA embedded in a 8-channel, 12-bit SAR
In Part 8, the system had a gain range of 1 to 128V/V. We found that at a gain of 16V/V accuracy was 0.006 percent, while producing 11.97 effective bits. The analog output swing was limited, but not enough to impact the amplifier and ADC offset and gain errors. Finally, the system had a very low-cost factor, reasonable power-down capability, and excellent noise performance.
In Figure 1, the signal starts at the ADC's multiplexer. The embedded PGA picks up the signal and applies a gain from 1 to 128. The PGA ports the signal to the input of the ADC op amp. The ADC op amp, in combination with the following R-C stage, drives the signal to the SAR-ADC's input. The input resistor/capacitor pair at the op amp (100Ω and 390pF) output provides resistive isolation between the amplifier and the 390pF capacitor, as well as a charge reservoir (the 390pF capacitor) for the converter's input (Ref. 1).
Noise generators in this circuit are the PGA, ADC op amp, and the 12-bit SAR-ADC. In terms of noise, the only component that changes with this system evaluation is the PGA. The change in PGA output noise with gain equals Equation 1:
In Equation 1,
- PGANOISE(RTO) = PGA output noise
- PGAGAIN = PGA gain
- PGANOISE(RTI) = PGA input noise = 12 nV/√Hz
- PGABW = PGA close loop bandwidth (depends on gain setting)
The ADC op amp noise and SAR-ADC noise are consistent across all gain changes. These noise values are equal to 13μVRMS and 460μVRMS, inclusive. Table 1 shows system noise versus PGA gain in Figure 1.
As the input multiplexer of the ADC (ADS7951) changes, there is a possibility that the PGA will see a step response. Consequently, the signal at the beginning of each conversion should be allowed ample time to settle. The settling time for the PGA in a gain of 16V/V is 2.6μs (typ.). Additionally, if the PGA gain changes, the device requires 16 clocks for the change. The programming time for this system will be worst case PGA settling/gain select times, which are collectively equal to 3μs.
The unity gain bandwidth of the amplifier (voltage feedback amplifier) is 38MHz. This wide bandwidth complements the SAR-ADC's conversion speed of 1Msps and acquisition time of 325ns. The settling time of this driver amplifier in a gain of one is equal to 0.5μs. Combining this with the settling time of the PGA you get Equation 2:
If a 30 percent guard band is added to this system, the settling time becomes 3.95μs or about 4μs.
In the SAR-ADC's conversion/mux switching algorithm, the converter samples the input signal and then immediately switches channels. This algorithm provides time for the PGA to settle and prepare for the next conversion.
The acquisition of the input signal occurs with the falling edge of chip select (CS) (Figure 2). During the following 16 clock pulses, the converter samples the input signal. Shortly after the signal acquisition, the multiplexer switches to the next setting. At the same time, serial data in (SDI) receives instruction for the next multiplexer setting, which is implemented after the following signal acquisition. In the following clocks, the ADC transmits the digital output word through the serial data out (SDO) pin.
When the PGA is on, its power dissipation is 7.5mW. If the PGA is put to sleep digitally or with the sleep pin, power dissipation is 20μW. The SAR-ADC has similar states. As the ADC is operating, its on power dissipation is 14mW. While the ADC is off, power dissipation is 5μW. Finally, this high-speed amplifier has no shut-down capability. The power dissipation of this device is 37.5mW. All power values stated above or typical numbers. Conclusion
This system's accuracy in terms of noise exceeds expectations. The OPA350/ADS7951 combination remains well under the one least significant bit (LSB) mark for a 12-bit system. The dynamic range again is very good, ranging from 5 volts (FSR) with a gain of 1 to 0.039V (FSR) with an analog gain of 128.
Referring to Figure 4, there is little difference between the DC specifications from this article's system and the system in “ADC Basics, Part 8.” The system from this article surpasses the other system in terms of noise and sampling speed.
- External components improve SAR-ADC accuracy, Baker, Oljaca, EDN, June 7, 2007.
- Download these data sheets: OPA350, PGA112, ADS7951.
- ADC Basics, Part 1: Does Your ADC Work in the Real World?
- ADC Basics, Part 2: SAR & Delta-Sigma ADC Signal Path
- ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs
- ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design
- ADC Basics, Part 5: Key ADC Specifications for System Analysis
- ADC Basics, Part 6: Key Op-Amp DC & AC Specifications
- ADC Basics, Part 7: Key Op Amp Frequency & Timing Specifications
- ADC Basics, Part 8: A 4-System Matrix With PGA + 12-bit SAR