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ADC/DAC card bridges analog and digital bandwidth divide

With the advent of artificial intelligence (AI) applications, multiple input and multiple output channels are being used at the edge to address the need for high bandwidth edge processing. A new FPGA Mezzanine Card (FMC) with low voltage differential signaling (LVDS) interfaces aims to facilitate that bandwidth ride.

The LXD31K4 unveiled by Logic-X is a 4-in-4-out card that provides four A/D channels, each with a data conversion rate of up to 310 mega-samples per second (Msps), and four D/A channels, each with a raw conversion rate of up to 310 Msps. All eight channels have 16-bit accuracy and deliver robust signal-to-noise (SNR) performance. Additionally, with up to 4x interpolation set by the user, the card can produce a signal with an update rate of up to 1.24 GHz.

Figure 1 The card comes with a reference design to help engineers accelerate their development programs. Source: Logic-X

The card can be incorporated into an embedded system on an as-is basis; it can also be used during the development and prototyping of a system-on-chip (SoC) design. The use of LVDS for data interfaces means that users can integrate the card with an FPGA without having to purchase and embed JESD204B-compliant interface cores for converters and receivers. Furthermore, the card’s LVDS pin-out is configured in a way that it works on most ‘partial implementations’ of the high-pin-count connectors on Xilinx development boards as well as Logic-X’s FPGA FMC carrier boards.

Besides edge processing, Logic-X is targeting the LXD31K4 card at high-speed data acquisition and playback, software-defined radio (SDR), and other applications requiring wide bandwidth conversion between analog and digital domains.

Figure 2 The LXD31K4 is sampling now, and volume availability is predicted for Q4 2021. Source: Logic-X

Logic-X also offers a 2-in-2-out version of this card; LXD31K2 features 16-bit resolution and utilizes LVDS interfaces. Both LXD31K4 and LXD31K2 come with a reference design that comprises detailed documentation, a Vivado IP integrator project, and IP cores that can be controlled from a software application over Ethernet or PCIe.

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