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ADC Digital Downconverter: A Complex Decimation Example Revisited

Over the last several months I have been describing the operation of the digital downconverter (DDC) that exists in the AD9680 which also exists in similar forms in the AD9684, AD9690, and AD9691. To coin a phrase my marketing engineer likes to us I have been “painting a picture.” I am working to convey to you as the reader the operation of the DDC so that you can be armed to use this digital functionality in your next system design. In this installment I’d like to revisit the example that was covered in my January blog post ADC Digital Downconverter: A Complex Decimation Example.

Recall from the example give that we have the AD9680-500 operating with an input clock of 491.52 MHz and an analog input frequency of 150.1 MHz. The AD9680 is set to use the digital downconverter (DDC) with a real input, a complex output, an NCO tuning frequency of 155 MHz, half band filter 1 (HB1) and half band filter 2 (HB2) enabled (total decimation rate equals four), and 6dB gain enabled. Since the output is complex the complex to real conversion block is disabled. Once again, let’s take a look at the basic diagram for the DDC, which is included below to serve as a refresher. Recall that the signal first passes through the NCO which shifts the input tones in frequency, then passes through the decimation filters, then through the gain block, and, in our case, bypasses the complex to real conversion.

DDC Signal Processing Blocks in the AD9680

DDC Signal Processing Blocks in the AD9680

Let’s revisit our look at using the frequency folding tool to understand the aliasing effects of the ADC. This will help to evaluate where the analog input frequency and its harmonics will be located in the frequency domain. In this example we have a real signal, a sample rate of 491.52 MSPS, the decimation rate is set to four, and the output is complex. At the output of the ADC, before entering the DDC, the signal appears as illustrated below with the frequency folding tool.

Signals at the Output of the ADC Illustrated by the Frequency Folding Tool

Signals at the Output of the ADC Illustrated by the Frequency Folding Tool

With an input sample clock of 491.52 MHz and an analog input frequency of 150.1 MHz, the fundamental input tone resides in the first Nyquist zone. The second harmonic of the input frequency at 300.2 MHz will alias into the first Nyquist zone at 191.32 MHz. The third harmonic at 450.3 MHz aliases to 41.22 MHz which is also in the first Nyquist zone. This is the state of the signal at the output of the ADC before it passes through any of the digital processing blocks in the DDC of the AD9680.

Let’s look at how the signals pass through the digital processing blocks inside the DDC. The plot is in terms of the input sample rate, 491.52 MSPS and the fS terms will be with respect to this sample rate. Let’s observe the general process. In this case the NCO frequency shift is not shown since the focus is on the decimation filtering. Once the signal in the complex (negative frequency) domain shifts beyond –fS /2 it will fold back around into the first Nyquist zone. Next the signal passes through the first decimation filter, HB2, which decimates by two. In contrast to my previous blog posts on this topic I am showing the decimation process including the filter response in this plot.

After the first decimation by a factor of two, the spectrum from fS /4 to fS /2 translates into frequencies between – fS /4 and DC. Similarly, the spectrum from – fS /2 to – fS /4 translates into the frequencies between DC and fS /4. The signal now passes through the second decimation filter, HB1, which also decimates by two (total decimation now is equal to four). The spectrum between fS /8 and fS /4 will now translate to the frequencies between – fS /8 and DC. Similarly, the spectrum between – fS /4 and – fS /8 will translate to the frequencies between DC and fS /8.

Notice that in this generic example the frequency planning could have been a little better since the content at the higher frequencies in the band are attenuated slightly by the HB2 decimation filter. This is given by the section for “Spectrum after Decimate by 4” in the figure. Also, note that the filter responses are an approximate representation of the actual response but may not exactly match the plots shown in the AD9680 data sheet. I am showing the responses here to give a representation to help us see where we should approximately expect frequencies to be attenuated. Notice that HB1 has a sharper rolloff than HB2. This can also be observed in the AD9680 data sheet plots of the decimation filter responses.

Signals As They Pass Through the DDC Signal Processing Blocks - Generic Example with Decimation Filtering

Signals As They Pass Through the DDC Signal Processing Blocks – Generic Example with Decimation Filtering

As we did previously we will take the information from the generic example and use it to look at actual frequencies. Let’s look at the plot of the ADC output in the frequency folding tool where we have an input sample rate of 491.52 MSPS and an input frequency of 150.1 MHz. Note: In my January blog post this tone was incorrectly shown at 153.1Mhz in the figure “Signals As They Pass Through the DDC Signal Processing Blocks.”) The NCO frequency is 155 MHz and the decimation rate is set to four (due to the NCO resolution the actual NCO frequency is 154.94 MHz). This results in an output sample rate of 122.88 MSPS. Since we are doing complex mixing we will need to include the complex frequency domain in our analysis. Please bear with me as the figure showing the frequency translations is quite busy but let’s try to work our way through the signal flow. Note that the decimation filter responses have been added and are shown in dark purple.

Signals As They Pass Through the DDC Signal Processing Blocks - Decimation Filtering Shown

Signals As They Pass Through the DDC Signal Processing Blocks – Decimation Filtering Shown

Spectrum after the NCO shift:

  • The fundamental frequency shifts from 150.1 MHz down to -4.94 MHz.
  • The image of the fundamental shifts from -150.1 MHz and wraps around to 186.48 MHz.
  • The 2nd harmonic shifts from 191.32 MHz down to 36.38 MHz.
  • The 3rd harmonic shifts from 41.22 MHz down to -113.72 MHz.

Spectrum after Decimate by 2:

  • The fundamental frequency stays at -4.94 MHz.
  • The image of the fundamental translates down to -59.28 MHz and is attenuated by the HB2 decimation filter.
  • The 2nd harmonic stays at 36.38 MHz.
  • The 3rd harmonic is attenuated by the HB2 decimation filter.

Spectrum after Decimate by 4:

  • The fundamental stays at -4.94 MHz.
  • The image of the fundamental stays at -59.28 MHz and is attenuated by the HB1 decimation filter.
  • The 2nd harmonic stays at -36.38 MHz and is attenuated by the HB1 decimation filter.
  • The 3rd harmonic is filtered and virtually eliminated by the HB1 decimation filter.

Let’s now revisit the actual measurement on the AD9680-500. The fundamental frequency is at -4.94 MHz. The image of the fundamental resides at -59.28 MHz with an amplitude of -67.112 dBFS which means that the image has been attenuated by approximately 66 dB. The second harmonic resides at 36.38 MHz and has been attenuated by approximately 10 to 15 dB. The third harmonic has been filtered sufficiently that it does not rise above the noise floor in the measurement.

FFT Complex Output Plot of Signal after DDC with NCO = 155 MHz and Decimate by 4

FFT Complex Output Plot of Signal after DDC with NCO = 155 MHz and Decimate by 4

From the FFT we can see the output spectrum of the AD9680-500 with the DDC set up for a real input and complex output with an NCO frequency of 155 MHz (actual 154.94 MHz due to the number of bits in the NCO tuning word), and a decimation ratio of four. As I had mentioned previously I have seen many questions related to this topic while supporting customers using the DDC in the AD9680. I hope these blog posts have provided some additional insight into the DDC operation and have equipped you as the reader to take on the challenge of understanding the output spectrum observed when using the DDC. The ultimate goal is to effectively frequency plan and generate a successful system design utilizing the available features of high speed ADC such as the AD9680. I look forward to continuing this discussion as we look at another tool at our disposal, VirtualEval, that can help us observe the DDC functionality without the need for actual hardware.

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