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ADC Digital Downconverter: A Complex Decimation Example

Over the last few blogs we’ve been looking at using the frequency folding tool available on the Analog Devices website. We looked at the basics of the frequency folding tool from Analog Devices in two previous blog posts, Analog Devices Design Tools: ADISimADC Frequency Folding Tool and Analog Devices Design Tools: Frequency Folding Tool Revisited along with an example in my last blog in November of this past year Analog Devices Design Tools: Frequency Folding Tool, A ‘Complex’ Example. We explored some basic examples of aliasing in an ADC. In addition we looked at how certain input frequencies and sample rates can result in a situation where tones alias to the same locations. In my most recent blog we looked at an example using the DDC in the AD9680-500 in complex output mode. Now, let’s add a little more to the example and increase the decimation ratio in the DDC to see the effects of frequency folding and translating when a higher decimation rate is employed along with frequency tuning with the NCO.

In this example we’ll look at the AD9680-500 operating with an input clock of 491.52 MHz and an analog input frequency of 150.1 MHz. The AD9680 will be set to use the digital downconverter (DDC) with a real input, a complex output, an NCO tuning frequency of 155 MHz, half band filter 1 (HB1) and half band filter 2 (HB2) enabled (total decimation rate equals four), and 6dB gain enabled. Since the output is complex the complex to real conversion block is disabled. Recall from my previous blog the basic diagram for the DDC, which is once again included below. In order to understand how the input tones are processed, it is important to understand that the signal first passes through the NCO which shifts the input tones in frequency, then passes through the decimation, through the gain block, and, in our case, bypasses the complex to real conversion.

DDC Signal Processing Blocks in the AD9680

DDC Signal Processing Blocks in the AD9680

Let’s also review the macro view of the signal flow through the AD9680 as well. As we discussed previously, the signal enters through the analog inputs, passes through the ADC core, into the DDC, through the JESD204B serializer, and then out through the JESD204B serial output lanes as illustrated below.

AD9680 Block Diagram

AD9680 Block Diagram

Once again we will use the frequency folding tool to help understand the aliasing effects of the ADC in order to evaluate where the analog input frequency and its harmonics will be located in the frequency domain. In this example we have a real signal, a sample rate of 491.52 MSPS, the decimation rate is set to four, and the output is complex. At the output of the ADC, the signal appears as illustrated below with the frequency folding tool.

Signals at the Output of the ADC Illustrated by the Frequency Folding Tool

Signals at the Output of the ADC Illustrated by the Frequency Folding Tool

With an input sample clock of 491.52 MHz and an analog input frequency of 150.1 MHz, the input signal will resides in the first Nyquist zone. The second harmonic of the input frequency will alias into the first Nyquist zone at 191.32 MHz while the third harmonic aliases to 41.22 MHz which is also in the first Nyquist zone. This is the state of the signal at the output of the ADC before it passes through the DDC.

Now let’s look at how the signals pass through the digital processing blocks inside the DDC. We will look at the signal as it goes through each stage and observe how the NCO shifts the signal and the decimation process subsequently folds the signal. We will maintain the plot in terms of the input sample rate, 491.52 MSPS and the fS terms will be with respect to this sample rate. Let’s observe the general process. The NCO will shift the input signals to the left. Once the signal in the complex (negative frequency) domain shifts beyond – fS /2 it will fold back around into the first Nyquist zone. Next the signal passes through the first decimation filter, HB2, which decimates by two.

In the figure, I am showing the decimation process without showing the filter response even though the operations occur together. This is for simplicity. After the first decimation by a factor of two, the spectrum from fS /4 to fS /2 translates into frequencies between – fS /4 and DC. Similarly, the spectrum from – fS /2 to – fS /4 translates into the frequencies between DC and fS /4. The signal now passes through the second decimation filter, HB1, which also decimates by two (total decimation now is equal to four). The spectrum between fS /8 and fS /4 will now translate to the frequencies between – fS /8 and DC. Similarly, the spectrum between – fS /4 and – fS /8 will translate to the frequencies between DC and fS /8. Although decimation is indicated in the figure the decimation filtering operation is not shown.

Signals As They Pass Through the DDC Signal Processing Blocks - Generic Example

Signals As They Pass Through the DDC Signal Processing Blocks – Generic Example

Now let’s study the example we’ve discussed above and look at the actual frequencies. Going back to the plot of the ADC output in the frequency folding tool, we will look at an input sample rate of 491.52 MSPS and an input frequency of 150.1 MHz. The NCO frequency is 155 MHz and the decimation rate is set to four (due to the NCO resolution the actual NCO frequency is 154.94 MHz). This results in an output sample rate of 122.88 MSPS. Since we are doing complex mixing we will need to include the complex frequency domain in our analysis. Please bear with me as the figure showing the frequency translations is quite busy but let’s try to work our way through the signal flow.

Signals As They Pass Through the DDC Signal Processing Blocks

Signals As They Pass Through the DDC Signal Processing Blocks

Spectrum after the NCO shift:

  1. The fundamental frequency shifts from 150.1 MHz down to -4.94 MHz.
  2. The image of the fundamental shifts from -150.1 MHz and wraps around to 186.48 MHz.
  3. The 2nd harmonic shifts from 191.32 MHz down to 36.38 MHz.
  4. The 3rd harmonic shifts from 41.22 MHz down to -113.72 MHz.

Spectrum after Decimate by 2:

  1. The fundamental frequency stays at -4.94 MHz.
  2. The image of the fundamental translates down to -59.28 MHz and is attenuated by the HB2 decimation filter.
  3. The 2nd harmonic stays at 36.38 MHz.
  4. The 3rd harmonic is attenuated significantly by the HB2 decimation filter.

Spectrum after Decimate by 4:

  1. The fundamental stays at -4.94 MHz.
  2. The image of the fundamental stays at -59.28 MHz.
  3. The 2nd harmonic stays at -36.38 MHz.
  4. The 3rd harmonic is filtered and virtually eliminated by the HB1 decimation filter.

Now let’s look at the actual measurement on the AD9680-500. We can see the fundamental resides at -4.94 MHz. The image of the fundamental resides at -59.28 MHz with an amplitude of -67.112 dBFS which means that the image has been attenuated by approximately 66 dB. The second harmonic resides at 36.38 MHz.

FFT Complex Output Plot of Signal after DDC with NCO = 155 MHz and Decimate by 4

FFT Complex Output Plot of Signal after DDC with NCO = 155 MHz and Decimate by 4

From the FFT we can see the output spectrum of the AD9680-500 with the DDC set up for a real input and complex output with an NCO frequency of 155 MHz (actual 154.94 MHz), and a decimation ratio of four. I encourage you to walk through the signal flow diagram to understand how the spectrum is shifted and translated. I see many questions related to frequencies that are in the output spectrum of the ADCs that are considered unexplainable. However, once the analysis is done and the signal flow is analyzed through the NCO and the decimation filters, it becomes evident that frequencies are just where they should be. I encourage and welcome questions as this is a complex (pardon the pun) operation to understand and follow. I hope this helps the next time you are working with an ADC that has integrated DDCs.

6 comments on “ADC Digital Downconverter: A Complex Decimation Example

  1. Klenner
    January 20, 2016

    Hi Jonathan,
    Its good to have DDCs now in ADCs. I was missing such features. Does the DDC here add to bit resolution (ENB)?
    Guenther

  2. jonharris0
    January 20, 2016

    Hi Klenner, thanks for you comments.  Indeed, the output of the DDC has 16 bits of resolution for the AD9680 (the ADC core itself is 14 bits).  Great question!

  3. Patbradley
    January 21, 2016

    nice one Its good to have DDCs now in ADCs. I was missing such features. Does the DDC here add to bit resolution

  4. jonharris0
    January 21, 2016

    Hi Klenner, inside the band of interest (within the DDC decimation filter bandwidth) the SNR is improved which results in an effective improvement in ENOB. You can see the ideal SNR improvement in Table 17 of the AD9680 data sheet.  For example with a real output and decimation ratio = 2 the ideal SNR improvement is 4 dB.  In practice I've seen generally between 3dB to not quite 4dB (depending on the IF since the jitter of the analog input and clock inputs have a larger impact at higher analog input freuencies).

  5. chaturian
    January 23, 2016

    nice post dis one good

  6. jonharris0
    January 29, 2016

    Thank you so much for the kind words chaturian.  I hope the information is useful for you.

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