Over the last few blogs we’ve been looking at DDCs and how frequencies are shifted and folded in the output spectrum. In the last blog, ADC Digital Downconverter: A Complex Decimation Example we started looking at the decimation filtering that is involved in the DDC digital processing. We looked at an example where we increased the decimation ratio in the DDC to see the effects of frequency folding and translating as a result of the decimation filtering. Let’s now take a closer look at the decimation filtering and how ADC aliasing influences the effective response of the decimation filtering.

Once again we will look at the AD9680 and use it as an example. In this case the normalized decimation filter responses are the same regardless of speed grade. The decimation filter responses simply scale with sample rate. In the example filter response plots included here the specific insertion loss versus frequency is not given exactly but is figuratively shown to illustrate the approximate response of the filter. These examples are intended to give a high level understanding of decimation filters responses in order to understand how frequency bands may or may not end up inside the pass band of the filter.

Recall that the AD9680 has four DDCs that consist of an NCO, up to four cascaded half band (HB) filters (which we will also refer to as decimation filters), an optional 6 dB gain block, and an option complex to real conversion block as illustrated in the figure below. Additionally, recall that the signal first passes through the NCO which shifts the input tones in frequency, then passes through the decimation, optionally through the gain block, and optionally through the complex to real conversion. DDC Signal Processing Blocks in the AD9680

In this blog we will focus on the DDC decimation filters when we operate the AD9680 with the complex to real conversion block enabled. This means the DDC will be configured to accept a real input and have a real output. In the AD9680 the complex to real conversion inherently shifts the input frequencies up in frequency by an amount equal to fS /4. Let’s take a quick look at how this process occurs using HB1 as an example. The figure below shows the low pass response of the HB1 filter. This is the response of HB1 showing the real and complex domain response. HB1 Filter Response – Real and Complex Domain Response

In order to understand the real operation of the filter it is important to first see how the filter operates when observing the real and complex spectrum which is available at the output of the ADC. The HB1 filter has a pass band of 38.5% of the real Nyquist zone. It also has a stop band that is 38.5% of the real Nyquist zone with transition band making up the remaining 23%. Likewise in the complex domain, the pass band and stop band each make up 38.5% (77% total) of the complex Nyquist zone with transition band making up the remaining 23%. As the figure illustrates the filter is a mirror image between the real and complex domains.

Now let’s take a look at what happens when we place the DDC into real mode by enabling the complex to real conversion. As I mentioned, enabling the complex to real conversion results in shift of fS /4 in the frequency domain. This is illustrated in the figure below which shows the frequency shift and the resulting filter response. Notice the solid lines and the dotted lines of the filter response. The solid line and shaded area indicates this is the new filter response after the fS /4 frequency shift (the resulting filter response cannot cross the Nyquist boundary). The dotted lines given for illustration to show the filter response that would exist if not for running into the Nyquist boundary. HB1 Filter Response – Real DDC Mode (Complex to Real Conversion Enabled)

Notice that the filter bandwidth remains unchanged between the two plots. The only difference is the fS /4 frequency shift. Notice however that in the complex mode plot we have 38.5% of Nyquist for the real portion of the signal and 38.5% of Nyquist for the complex portion of the signal. In the real mode plot we now have 77% of Nyquist for the real signal and the complex domain has been discarded. In common industry terms the real or “I” portion remains and the complex or “Q” portion is discarded. The filter response remains unchanged apart from the fS /4 frequency shift. Also, notice as a product of this conversion the decimation rate is now equal to one. The effective sample rate is still fS but instead of the whole Nyquist zone there is only 77% of available bandwidth in the Nyquist zone.

Now, we will take a look at the filter responses of and how aliasing of the ADC input frequencies impacts the effective decimation filter responses. First, we will continue looking at the example above with the HB1 filter. The actual frequency response of HB1 is given by the solid blue line in the figure. The dashed line represents the effective aliased response of HB1 due to the aliasing effects of the ADC. Due to the fact that frequencies input into 2nd , 3rd , 4th , etc. Nyquist zones, the HB1 filter response is effectively aliased into these Nyquist zones. For example a signal residing at 3fS /4 will alias into the first Nyquist zone at fS /4. Similarly, a frequency at 7fS /4 will also alias into the first Nyquist zone at fS /4. It is important to understand that the HB1 filter response resides only in the first Nyquist zone and that it is the aliasing of the ADC that results in the effective response of the HB1 filter appearing to be aliased into the other Nyquist zones. Recall also that we are looking at real mode operation for the DDC so the complex domain data has been discarded. HB1 Effective Filter Response Due to ADC Frequency Aliasing (Decimation Ratio = 1)

Now let’s look at the case where we enable HB1 and HB2. This results in a decimation ratio of two. Once again, the actual frequency response of the HB1 + HB2 filters is given by the solid blue line. Enabling both HB1 and HB2 filters results in an available bandwidth of 38.5% of the Nyquist zone. Once again, notice the aliasing effects of the ADC and its impact on the combination of HB1 + HB2 filters. A signal that appears at 7fS /8 will alias into the first Nyquist zone at fS /8. Likewise a signal at 5fS /8 will alias into the first Nyquist zone at 3fS /8. HB1 + HB2 Effective Filter Response Due to ADC Frequency Aliasing (Decimation Ratio = 2)

Next we will look at the case where HB1, HB2, and HB3 are enabled with real DDC mode. In this case the decimation ratio is equal to four. Here we see that the available bandwidth of 38.5% of fS /4. For simplicity and ease of viewing I have condensed the figure to more easily show the whole filter response. Notice that there is approximately 100 dB of rejection from just past fS /8 through the end of the first Nyquist zone. Once again, the effective aliased response of the HB1 + HB2 + HB3 filters is given by the dashed line. Notice also that as we increase the number of decimation filters used the available bandwidth decreases. HB1 + HB2 + HB3 Effective Filter Response Due to ADC Frequency Aliasing (Decimation Ratio = 4)

The last combination of filters that we will look at is HB1 + HB2 + HB3 + HB4 which has all the decimation filters in the AD9680 enabled and results in a decimation ratio of eight when operating the DDC in real mode. This case is quite similar to the previous case but just scaled to reflect the larger decimation ratio. In this case we have an available bandwidth of 38.5% of fS /8. In this case we have approximately 100 dB of rejection from just past fS /16 through the end of the first Nyquist zone. Once again, this response is effectively aliased into the upper Nyquist zones. HB1 + HB2 + HB3 + HB4 Effective Filter Response Due to ADC Frequency Aliasing (Decimation Ratio = 8)

Let’s take a closer look at the three filter responses for decimation ratios of two, four, and eight. If we take these plots and copy the response from 0 to fS we can paste this response exactly into the frequencies between fS and 2 fS . Likewise the response can be pasted into the frequencies between 2 fS and 3 fS . This repetitively carries on through all Nyquist zones in this manner. Now the questions come inevitably which include: “Why do we decimate?” and “What advantage does it offer?” The answer is actually pretty simple: “It depends.” Different applications have different requirements that can benefit from decimation of the ADC output data. One motivation is to gain signal to noise ratio (SNR) over a narrow band of frequency that resides in an RF frequency band. For example, let’s say we have a 20 MHz frequency band that resides at 1.7 GHz.

If using an RFADC with a sample rate of 1.0 GSPS such as the AD9680 without a DDC to capture this signal then a 500 MHz Nyquist zone is processed to get a 20 MHz frequency band at 1.7 GHz. In contrast, using the DDC with HB1 + HB2 + HB3 + HB4 filters enabled filters the available signal bandwidth down to 48.125 MHz and the Nyquist bandwidth down to 62.5MHz. The 48.125 MHz of available signal bandwidth is sufficient to capture the desired 20 MHz band. The 62.5MHz Nyquist zone is much less bandwidth to process and results in lower output lane rates across the JESD204B interface which allows the use of a lower cost FPGA. Of course, in this example the NCO would also need to be tuned properly, but for simplicity we will just focus on the decimation filters. By using all four decimation filters the DDC can realize processing gain and improve the SNR by up to 10 dB. This gives more dynamic range for the input signal making it easier to capture the desired signal with high fidelity. In Table 1 below we can see the available bandwidth, decimation ratio, output sample rate, and the ideal SNR improvement offered by the different decimation filter selections.

Table 1 This gives us a pretty good picture of the real mode operation of the DDC with the decimation filters enabled. I’ve included just a few reasons why the DDC is useful. There are many other advantages as well. A few others include the DDC implemented in the ADC is more power efficient than a DDC implemented in an FPGA (although less flexible) and the output data rate in the JESD204B interface can be significantly reduced both of which allow for the use of a lower cost FPGA. Stay tuned for the next blog where we will continue looking at the DDC operation and take a look at the decimation filter responses when operating the DDC in complex mode.

1. blatech
May 27, 2016

I guess this is similar to inductor chokes, which converts high frequency ac into dc.

2. jonharris0
May 31, 2016

Hi there blatech.  I am not sure I see the parallel but thank you for your comment.  I appreciate you reading my blog.

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