There can be significant system performance improvements when a differential input ADC is used, compared to single-ended ADC. No doubt single-ended ADCs may be available at a lower cost compared to differential ADCs and are even a good fit for some applications. However, in some applications single-ended ADCs cannot be used to meet required performance. Sometimes the system designer has an option to select between the two without any cost difference.
For example, SoCs like the PSoC 1 family from Cypress integrate different type of ADCs that support both input configurations. With both input configurations available, it helps to understand their differences so the most appropriate configuration can be chosen to best meet the various requirements of the system.
Single-ended ADC: Single-ended ADCs each have one input (not to be confused with input channels) that connects to the signal that needs to be converted to digital. The signal is referenced to either GND or some other fixed voltage reference. Figure 1 shows the typical representation of a single-ended ADC.
Differential ADC: In differential ADCs, two inputs — the inverting input (Vin -) and non-inverting input (Vin +) — are available to the ADC. Unlike single-ended ADCs, the input signal of differential ADCs is not referenced to a fixed voltage reference. Figure 2 shows the typical representation of a differential ADC. To simplify analysis, it is assumed that the input voltage is “center-tapped” with half of the voltage above ground and half below ground. In actuality, the input voltage need not be centered about ground and, as mentioned above, need not actually be ground referenced. However, attention must be paid to the acceptable input common-mode voltage range of the ADC.
The primary advantage of differential ADCs is high common-mode noise immunity compared to single-ended ADCs. This noise immunity is due to: 1) the same noise being coupled on both the inverting and non-inverting input signals of the ADC; and 2) this noise is rejected by common-mode rejection capabilities of the differential ADC.
In differential ADCs, both input signals are physically run in parallel with each other. Thus the same amount of noise gets coupled into both the signals. Also, when both signals are running in parallel and run the same distance (same trace/wire length), they are in the same phase when they reach the ADC. As noise coupled on both signals has the same amplitude and same phase, it gets rejected to provide very high noise immunity. This high noise immunity makes differential ADCs a best fit in the applications where the output signal from a sensor is very small and/or noise in the system is very high.
One such example is load-cell interfacing used in industrial control applications. With a load-cell, the output signal is differential in nature and the signal voltage swing is only a few millivolts. The signal is riding on top of noise that may be a few volts in amplitude — but the noise is common mode.
One may think of using a differential to single-ended stage like an instrumentation amplifier or a transformer before applying a differential input signal to a single-ended ADC and hope to achieve good noise performance by virtue of rejection of coupled noise on the long wires by this converter stage. However, this will not provide the same performance that could be achieved using a differential ADC.
One reason is that some noise may get coupled on the signal when it travels from the differential to single-ended converter. In addition, the ADC offset and the offset of the converter stage will play a major role and must be removed for accurate measurement. Generally, additional signal conditioning stages add noise that reduces the overall SNR of the signal chain. There are ADCs that have internal gain capabilities that provide better noise performance compared to external amplifiers. Thus it is a good practice to avoid an external gain stage/differential to single-ended converter.
In differential ADCs, SNR is also improved because of the change in the dynamic range. The dynamic range of a differential ADC is given by Vin – ± Vin +. In these ADCs, generally both inputs can range from Vss to Vdd (low supply rail to high supply rail). This makes the dynamic range twice as much as in case of single-ended ADC – that is 2⋅Vdd .
Equation 1 gives the SNR for an ADC.
In case of a differential ADC, the signal amplitude can be twice as high compared to a single-ended ADC. Thus the SNR is improved by 6dB just because of a higher dynamic range in the differential ADC.
Also, any DC offset (limited only by common-mode voltage) can be provided for signals that are too small and have an amplitude close to the lower supply rail, or for signals that have a voltage below the ADC ground. This DC offset gets removed by the common-mode rejection characteristics of differential ADCs. It also reduces significant overhead that would have been required to remove the DC offset if a single-ended ADC was used.
The only major drawback of differential input ADCs is the reduced number of input channels that can be implemented using a given number of pins. Because they use two pins per input, differential ADCs can have only half the number of channels compared to single-ended ADCs with same number of pins. This may not be an issue when many pins are available. However, if limited pins are available on the package, this may become a concern. Also consider that ADCs that support both single-ended and differential mode may support different sample rates in both modes. It is a good idea to check if the ADC meets required sample rate in the required conversion mode and resolution.
For the most recent ADC Guide article, please see: ADC Guide, Part 11: ADC Noise – 2, SINAD, ENoB
About the authors:
Sachin Gupta is working as Senior Applications Engineer in the PSoC 1 Applications group with Cypress Semiconductor. He holds a Bachelor’s degree in electronics and communications from Guru Gobind Singh Indraprastha University, Delhi. He has several years of experience in mixed signal application development. He can be reached at email@example.com.
Akshay Phatak is an Applications Engineer with Cypress Semiconductor. He holds a Bachelor's degree in electronics and telecommunications from the College of Engineering, Pune, India. He likes to work on mixed-signal embedded systems. He can be reached at firstname.lastname@example.org.