The input range of a single-supply ADC can be extended with three resistors and some design formulas. The formulas are derived and presented. The typical circuit for which the formulas apply is shown below.

As is typical of single-supply ADCs, the ADC input voltage, *v _{I} * , ranges from 0 V at –fs to

*V*at +fs.

_{R}**Two-resistor bipolar-to-unipolar conversion**

To make the circuit input voltage, *v _{X} * , have a bipolar range, the common method is to set

*R*=

_{R1}*R*and omit

_{X}*R*. Then the range is found from the superposition of voltages at each end of the divider having an attenuation of

_{R2}By superposition,

The input voltage range of *v _{X} * is then found by setting

*v*=

_{I}*V*whenever

_{R}*v*=

_{X}*v*(+fs) and

_{X}*v*= 0 V for

_{I}*v*=

_{X}*v*(–fs):

_{X}Subtract the second equation from the first and solve for *T _{X} * ,

where Δ*v _{X} * is the full bipolar range of the input voltage. For the simple method, set

*R*=

_{R1}*R*. The result is that

_{X}*T*= 1/2 and Δ

_{X}*v*= 2•

_{X}*V*. The ADC input voltage is then

_{R}The input voltage has been divided by two and the ADC input offset to midrange. The result is that *v _{X} * now has a range of –

*V*to +

_{R}*V*. For the given ADC, the range is now +/-

_{R}*V*= +/-4.1 V.

_{R}**General bipolar-to-unipolar conversion**

This simple method can be generalized by adding a third resistor, *R _{R2} * , and deriving the design formulas for a given

*v*range. The resistors

_{X}*R*and

_{R1}*R*form a divider which can be thevenized as shown above. The divider attenuation is

_{R2}and the Thevenin series resistance is

*T _{X} * becomes

Again, the ADC input range will be set to

The superposition equation for the divider is

Solving for *v _{X} * ,

Following the previous derivation, equations for the limits of the range are

and the second equation, when subtracted from the first and solved, results in the formula for *T _{X} * ,

It is the same as for the simple case. The derivation becomes more general when *T _{X} * is substituted into either range-limit equation and solved for

*T*,

_{R}At *v _{X} * (zs) = 0 V, the ADC input is the thevenized reference voltage,

*T*•

_{R}*V*, divided in reverse by the

_{R}*T*divider,

_{X}The same voltage results from a positive |*v _{X} * (–fs)| applied to the TX divider with the thevenized V

_{R}set to zero.

The ADC *v _{I} * range is offset positive from 0 V by

*V*/2. This causes the value of

_{R}*v*for

_{X}*v*=

_{I}*V*/2 to be offset according to the divider superposition formula solved for

_{R}*v*,

_{X}Substituting the ADC center-scale value of *v _{I} * =

*V*/2,

_{R}For a symmetrical range of *v _{X} * around

*v*=

_{X}*v*(zs) = 0 V,

_{X}Then substituting into *T _{R} * ,

We now have the equations leading to a design procedure that result in resistor values.

**Design procedure**

To design the divider circuit for a symmetric input range, given *V _{R} * ,

*v*(+fs), and

_{I}*v*(–fs), then choose Δ

_{I}*v*and either

_{X}*R*(for the dominant input resistance) or

_{X}*R*. Then apply these design formulas in the following sequence:

_{R1}For the example of the circuit given in the above diagram, *V _{R} * = 4.1 V,

*v*(+fs) =

_{I}*V*,

_{R}*v*(–fs) = 0 V, and

_{I}*R*= 12.00 kΩ, 0.1 %. The desired range for

_{R1}*v*is about Δ

_{X}*v*= 61.5 V. This voltage is exactly 15•

_{X}*V*, which makes

_{R}*T*= 1/15. For a symmetric bipolar

_{X}*v*range,

_{X}Then solving for *R _{X} * ,

A decade value is chosen for *R _{X} * because it is close. Then solving for

*R*,

_{R2}By choosing a 1 % value for *R _{R2} * and a decade value for

*R*, then

_{X}*R*= (12.00 kΩ || 14.0 kΩ) = 6462 Ω. The divider values become

_{R}The equation for *v _{I} * is now

Solving for *v _{X} * ,

By substituting the range limits on *v _{I} * , the range limits of

*v*have become

_{X}The input voltage corresponding to the ADC midrange voltage is *v _{X} * (cs) = –390.6 mV. And the ADC input voltage corresponding to the zs (0 V) input is

*v*(zs) = 2.074 V. This voltage is slightly higher than

_{I}*V*/2 = 2.05 V. The offsets and asymmetry of the

_{R}*v*range is caused by choosing a 1 % value for

_{X}*R*. The change in

_{R2}*R*affects Δ

_{X}*v*but is not the cause of the asymmetric input range.

_{X}*R*affects

_{X}*T*and once it is determined, then for a symmetric range,

_{X}*T*is determined by it, as is

_{R}*R*for a given

_{R2}*R*.

_{R1}Bipolar voltages exceeding the ADC input range are not infrequently measured by single-supply ADCs, and the above design procedure is likely to be useful for design. The derived formulas can be applied for other choices of ADC input range and do not necessarily require a symmetric input range, though the design procedure must be modified slightly to accommodate the most general case.

Dennis

I did a Design Idea in Electronic Design of a similar configuration “Use Excel To Calculate A-D Level-Shifter Resistor Values“. ED seesm to have dropped their archive of the Excel worksheet, but I have it stored here. I actually recently discussed in in my blog on MCU Designlines “Digital Level Shifting“.

I did a Design Idea in Electronic DesignI originally submitted the design idea to EDN. It was refused on the grounds that the resistor network may overload current capabilty of the source of the signal. I adjusted the calculation to include this current, but it was still refused.

I am no longer bitter, but I thought I should add the caution here.

Or there are IC's that do this with precision out of the box from TI and Analog Devices. INA159, AD8275, etc.

How did the equations you used in your computer program compare to the ones in this article? If they are equivalent (or even the same), then the resistances can be scaled for acceptably light loading. So I don't see where source loading should be a factor for such a computation. The designer chooses what the input resistance should be and scales the resistors accordingly.

If the cost of an IC that is a functional equivalent is more than the cost of 3 resistors, why not use the resistors? Perhaps the IC is precision trimmed and smaller in size than the 3 Rs. That might justify IC use. In many cases not involving demanding dynamic performance, I suspect the resistor solution is optimal.

The INA159 provides +/-0.024% accuracy (12-bit) with 1ppm/degC in 3mm x 5mm (15mm area). 1k price is $1.70ea.

0.02% resistors in Digi-Key are $1.11ea@5k.

Just as a point of reference, 0.1% resistors in Digi Key $0.04ea@5k. 1.6×0.8mm, 3 resistors (3.9mm area).