The input range of a single-supply ADC can be extended with three resistors and some design formulas. The formulas are derived and presented. The typical circuit for which the formulas apply is shown below. As is typical of single-supply ADCs, the ADC input voltage, vI , ranges from 0 V at –fs to VR at +fs.

Two-resistor bipolar-to-unipolar conversion
To make the circuit input voltage, vX , have a bipolar range, the common method is to set RR1 = RX and omit RR2 . Then the range is found from the superposition of voltages at each end of the divider having an attenuation of By superposition, The input voltage range of vX is then found by setting vI = VR whenever vX = vX (+fs) and vI = 0 V for vX = vX (–fs): Subtract the second equation from the first and solve for TX , where ΔvX is the full bipolar range of the input voltage. For the simple method, set RR1 = RX . The result is that TX = 1/2 and ΔvX = 2•VR . The ADC input voltage is then The input voltage has been divided by two and the ADC input offset to midrange. The result is that vX now has a range of –VR to +VR . For the given ADC, the range is now +/-VR = +/-4.1 V.

General bipolar-to-unipolar conversion
This simple method can be generalized by adding a third resistor, RR2 , and deriving the design formulas for a given vX range. The resistors RR1 and RR2 form a divider which can be thevenized as shown above. The divider attenuation is and the Thevenin series resistance is TX becomes Again, the ADC input range will be set to The superposition equation for the divider is Solving for vX , Following the previous derivation, equations for the limits of the range are and the second equation, when subtracted from the first and solved, results in the formula for TX , It is the same as for the simple case. The derivation becomes more general when TX is substituted into either range-limit equation and solved for TR , At vX (zs) = 0 V, the ADC input is the thevenized reference voltage, TR VR , divided in reverse by the TX divider, The same voltage results from a positive |vX (–fs)| applied to the TX divider with the thevenized VR set to zero.

The ADC vI range is offset positive from 0 V by VR /2. This causes the value of vX for vI = VR /2 to be offset according to the divider superposition formula solved for vX , Substituting the ADC center-scale value of vI = VR /2, For a symmetrical range of vX around vX = vX (zs) = 0 V, Then substituting into TR , We now have the equations leading to a design procedure that result in resistor values.

Design procedure
To design the divider circuit for a symmetric input range, given VR , vI (+fs), and vI (–fs), then choose Δ vX and either RX (for the dominant input resistance) or RR1 . Then apply these design formulas in the following sequence: For the example of the circuit given in the above diagram, VR = 4.1 V, vI (+fs) = VR , vI (–fs) = 0 V, and RR1 = 12.00 kΩ, 0.1 %. The desired range for vX is about ΔvX = 61.5 V. This voltage is exactly 15•VR , which makes TX = 1/15. For a symmetric bipolar vX range, Then solving for RX , A decade value is chosen for RX because it is close. Then solving for RR2 , By choosing a 1 % value for RR2 and a decade value for RX , then RR = (12.00 kΩ || 14.0 kΩ) = 6462 Ω. The divider values become The equation for vI is now Solving for vX , By substituting the range limits on vI , the range limits of vX have become The input voltage corresponding to the ADC midrange voltage is vX (cs) = –390.6 mV. And the ADC input voltage corresponding to the zs (0 V) input is vI (zs) = 2.074 V. This voltage is slightly higher than VR /2 = 2.05 V. The offsets and asymmetry of the vX range is caused by choosing a 1 % value for RR2 . The change in RX affects ΔvX but is not the cause of the asymmetric input range. RX affects TX and once it is determined, then for a symmetric range, TR is determined by it, as is RR2 for a given RR1 .

Bipolar voltages exceeding the ADC input range are not infrequently measured by single-supply ADCs, and the above design procedure is likely to be useful for design. The derived formulas can be applied for other choices of ADC input range and do not necessarily require a symmetric input range, though the design procedure must be modified slightly to accommodate the most general case.

1. antedeluvian
October 7, 2014

Dennis

I did a Design Idea in Electronic Design of a similar configuration “Use Excel To Calculate A-D Level-Shifter Resistor Values“. ED seesm to have dropped their archive of the Excel worksheet, but I have it stored here. I actually recently discussed in in my blog on MCU Designlines “Digital Level Shifting“.

2. antedeluvian
October 7, 2014

I did a Design Idea in Electronic Design

I originally submitted the design idea to EDN. It was refused on the grounds that the resistor network may overload current capabilty of the source of the signal. I adjusted the calculation to include this current, but it was still refused.

I am no longer bitter, but I thought I should add the caution here.

3. bearchow
October 7, 2014

Or there are IC's that do this with precision out of the box from TI and Analog Devices. INA159, AD8275, etc.

4. D Feucht
October 9, 2014

How did the equations you used in your computer program compare to the ones in this article? If they are equivalent (or even the same), then the resistances can be scaled for acceptably light loading. So I don't see where source loading should be a factor for such a computation. The designer chooses what the input resistance should be and scales the resistors accordingly.

5. D Feucht
October 9, 2014

If the cost of an IC that is a functional equivalent is more than the cost of 3 resistors, why not use the resistors? Perhaps the IC is precision trimmed and smaller in size than the 3 Rs. That might justify IC use. In many cases not involving demanding dynamic performance, I suspect the resistor solution is optimal.

6. bearchow
October 9, 2014

The INA159 provides +/-0.024% accuracy (12-bit) with 1ppm/degC in 3mm x 5mm (15mm area). 1k price is \$1.70ea.

0.02% resistors in Digi-Key are \$1.11ea@5k.

Just as a point of reference, 0.1% resistors in Digi Key \$0.04ea@5k. 1.6×0.8mm, 3 resistors (3.9mm area).

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