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ADC Input Resistance: A Question of Sampling

One of our field applications guys wanted to know the input resistance of one of our ADCs; a customer had asked him and couldn’t find the data. Like most integrated ADCs these days, this one (the SAR ADC in our PSoC 4 family of devices) has a switched-capacitor front end and, in the interests of maximum flexibility and minimum power consumption, we don’t fit an input buffer amplifier. We let you do that if you want, but sometimes people want to ‘go native’ and feed the ADC directly.

In the interests of finding a value to put in the datasheet (yes, there was already a number in the datasheet…) we use the classic expression for the equivalent resistance of a switched capacitor C that is being charged from a voltage of V at a rate of F times a second. It’s pretty easy to see that Q = CV is the amount of charge transferred each time we charge the cap. This means that in one second, the total charge transferred is CVF . But charge per second is just the current I , so I = CVF . And the equivalent resistance R equals V/I so, by the power of algebraic rearrangement, we finally get V/I = R = 1/CF . And I didn’t even need to open an equation editor.

But it’s always worth looking deeper. I wanted to know why the customer wanted to know what the input resistance of the ADC was. “Well, he wants to know how much attenuation he’ll get when he feeds the ADC from a transducer with a particular output resistance”, quoth my colleague.

Now, dear reader, pay close attention to that little red light that just started flashing in your peripheral vision. It’s a warning light, and I’ve willed it into being to alert you to an elephant-shaped issue in the room.

The calculation we did tells you what the mean current into the switched capacitor at the ADC’s input is. If you are monitoring the voltage on that switched capacitor using an average-responding meter with a time constant very much longer than the period of the switching clock, this is what you’ll read.

But, duh. Most of the time you’re not monitoring that voltage with a clunky old meter. You’re monitoring it with the ADC . And the ADC examines the voltage on that capacitor in a very different way. To figure out what result you’ll get if you look at the actual data, we need to dip into the concept of sampling aperture.

Broadly speaking, an ADC with a switched-capacitor input stage spends some time charging up its input capacitor to the applied input voltage. This is the part of the process that you can ‘see’ from the outside. Then it flips the capacitor connection over in order to disgorge the charge into the inner workings of the ADC, which then does some algorithmic clockwork and spits out a digital value. This part doesn’t affect the outside world.

The time that the input capacitor is given to charge up is the aperture time. In order for the ADC to meet expectations of how accurately it can capture an input voltage, the cap needs to charge up to pretty close to the applied voltage. Now, what affects that charging process? In essence, we can assess it if we know the value of the capacitance, the time that the ADC hardware gives us for the charging, and – the resistance of the source of that input voltage. As we increase the source resistance, the time constant of the RC network formed with the ADC’s input capacitance lengthens. We all know that an RC circuit charges up according to some pretty fundamental principles. If the input capacitor hasn’t quite “got there” by the end of the sampling aperture period, the charge transferred to that cap will be lower than it should be, and therefore so will the final digital rendition of the input signal.

So, if we make the source resistance too high, the value of the digital code falls off. This is exactly what we would expect if the ADC had a finite input resistance, ‘pulling’ the signal down!

So now, let’s have a go at calculating the equivalent input resistance R of the ADC as seen in the output data itself. I hope you’ll be able to follow the following expression (again, without the benefit of an equation editor): r/(R+r) = 1-exp(-t/rC) , where r is the source resistance we’re using and t is the aperture time set in the ADC hardware.

Now some more of that lovely algebra (try it, it’s good for you) results in R = r(exp(t/rC)-1) . This shows that the apparent input resistance R is actually a function of the source impedance r you use to test it! How the heck do you untangle that?

Well, the secret is to decide what sort of accuracy you want to get from your converter. Let’s say that it’s a 12-bit converter, and you want the effect of the input impedance to be limited to half an LSB of error.

Now the error we’re looking for is r/(r+R) , which is pretty close to r/R and we want this to be 2-13 in this case. So this means that exp(t/rC) = 8192 , and taking logs of both sides we get t = 9.01rC (the rule of thumb for 12-bit 0.5-LSB settling being t = 9rC , easy to remember).

So this means that if we are stuck with a source resistance of r , we must set the aperture time of the ADC to be equal to 9rC in order that the effective input resistance is 8192r , i.e. such that we get only 0.5 LSB error from this source.

See what I did there? I turned the question round from “what is the input resistance?” to “how do we set up the ADC so that the error due to the apparent input resistance is always 0.5 LSB or less?”.

Now, it stands to reason that all this wouldn’t be much good if you didn’t have fine control over the aperture time of your ADC. Panic not! Commercial message alert: the SAR (successive approximation register) ADC in the PSoC 4 family of parts from Cypress has a huge adjustment range, accessible from the virtual ‘component’ that you use to configure and connect the ADC in the PSoC Creator IDE.

So, with a judicious combination of aperture time setting and ADC clock selection, we were able to get our customer up and running, his head cleared of worries over attenuation. Irresistible!

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