ADC Noise: A Second Look, Part 2

In the previous part of this blog (ADC Noise: A Second Look, Part 1) we looked at some of the ways noise can sneak into an ADC through its input and output connections. We'll continue by looking at the digital I/O lines and finish by looking at the ground connections.

The digital I/O lines of an ADC are also doorways for noise. There are several different functions for digital I/O and therefore different ways for noise to enter the ADC through each. The most obvious is the digital output interface. This is much more of a concern on ADCs with CMOS outputs due to their single-ended implementation.

Typically, ADCs with LVDS outputs or those that employ the serial JESD204B interface are much more immune to noise coupling. In addition to the digital outputs, there is an increasing amount of digital circuitry within the ADC itself that offers some potential entry points for noise through the control lines. With this increased digital content comes the need to provide I/O for these functions. Sometimes the additional I/O is done through the SPI (serial port interface). And sometimes, the SPI isn't quite able to handle all that's required.

A side note about SPI: Not only is the SPI a potential noise doorway, it can cause other conversion problems. Various recommendations say to not access the SPI of the ADC while in system operation (while conversions are taking place).

Other I/O include mode control, power-down, standby, over range indicator, synchronization pins, etc. These are all things to pay attention to and make sure proper decoupling is used in addition to good layout practices to avoid noise coupling.

Probably the most overlooked doorway (and I certainly overlooked this myself last time) is the ground of the ADC. And please note that when I say ground, I'm referring to circuit common. Note also that there are usually multiple ground connections such as analog ground and digital ground. For these two grounds, you sometimes need to consider where they are bonded or tied together. This is a topic for another blog sometime.

Ground is often thought of as naturally being a solid reference point. However, the ground is not always a stable reference point and can allow noise to enter the ADC. It is important to pay attention to the ground planes in the system design and layout in order to make sure there is sufficient plane area without breaks and with sufficient ground vias to allow for proper current return paths. It is imperative to consider all the current return paths in the design rather than to assume the ground is a stable reference point.

Without proper system design, noise can be present in the ground plane and can make its way into the ADC. Have a look at Bill Schweber's blog, (Under)standing Your Ground, and Bruce Archambeault blog, The Ground Myth, for some additional insight into the topic of ground, ground currents, ground impedance, and E-M fields. Bruce specifically discusses how the current flowing in a trace interacts with the ground or power plane in the layer right below the trace and how that may cause problems.

Current that is flowing somewhere other than where you think it will or should be flowing is not actually noise in the strictest sense, but it is clearly trouble.

Now I think we are armed with all the information we need to properly consider the noise doorways into an ADC. Let's continue our journey and begin looking at each one of these doorways in more detail. Thanks once again for the great comments; please keep them coming. I think we will have lots of fun and will learn much about the different ways noise can enter an ADC and what we can do to combat the noise so we have a good system design.

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11 comments on “ADC Noise: A Second Look, Part 2

  1. amrutah
    November 15, 2013

    Jonathan, Thanks for the ADC noise series and want to dig deep into the Noise issues of this sub-system. Hope we discuss more about how these effect the quant noise and LSB error.

        As you rightly said, the internal digital networks used for sampling, synchronising, PM logic, decoupling capacitors need to be planned properly so that we don't introduce additional noise.


  2. amrutah
    November 15, 2013

    “It is imperative to consider all the current return paths in the design rather than to assume the ground is a stable reference point.”

       This is exactly the point that needs to be thought off.  The ground and Power plans have to be least resistive so that the rsulting noise voltage is as minimum as possible.  The ground network even though star connected or whatever network should have a low resistive current path.

  3. Davidled
    November 15, 2013

    The method to use interior layers to route signal would reduce noise using through-hole and Blind/Buried vias unless cost and size is issue in the view point of power distribution. PCB material would contribute to noise reduction.

  4. Netcrawl
    November 16, 2013

    The ground and power planes are key factors in reducing noise voltage, proper design and good layout make this possible, we starting project we need to take a closer look at this matter, the ground is our reference point. 

  5. Davidled
    November 17, 2013

    Delay and Noise

    There are a delay (latency) between the time a signal is sampled and the time the digital output is generated in ADC. This delay causes the error of the presented data value. This latency would be critical factor in the high speed communication application. If amplifier is used in the signal condition of ADC, this improves signal paths, but increases noise which means noise would be increased with signal level. Therefore engineer might consider ways to design the circuit with board in order to achieve the minimization of noise.   

  6. jonharris0
    November 18, 2013

    Very good points here by all.  Thanks for the many great comments.  I hope to start looking at these concepts as we talk about all the noise entry points in my upcoming blogs.

  7. amrutah
    November 18, 2013


     “There are a delay (latency) between the time a signal is sampled and the time the digital output is generated in ADC. This delay causes the error of the presented data value…”

       This delay would be present for all the samples of the input ADC signal, why do you say that this will case error instead of time-shifted digital output.

  8. Davidled
    November 18, 2013

    The goal is of ADC is to get the correct digital value in corresponding analog data as removing noise and delay. As one of factors, the delay could be minimized as updating decoding process inside ADC.

  9. yalanand
    November 30, 2013

    @Jonathan, Thanks for the post. I want to know, if the number of  output  of bits  of analog to digital converter are increased ,how it will effect on the noise of the system and are there any advanced techniques to remove noise like this?

  10. jonharris0
    December 12, 2013

    @yalanand, I don't think I've seen any evidence that suggests the number of outputs bits has an adverse impact on system noise.  Are you inferring that an increase in the number of LVDS lines might cause this?  I would suspect this to be the case.  The potential is increased for noise coupling onto the data lines since there are more output bits, but since most converters are LVDS today (and moving to JESD204B) the differential nature of the signals makes them more immune to noise.  In addition, on converters with JESD204B there is a scrambling option that can be enabled (providing both the ADC and FPGA support it) that would help with any EMI that may be produced by the data lines.  Hope this helps!

  11. jonharris0
    December 12, 2013

    I would clarify just one point here.  The return currents in a system will find the path of least inductance back to the source.  This is important to remember in high frequency designs.  In very low frequency designs, it is the path of least resistance but as we move up in frequency the return paths are defined by where the current finds its least inductive path.  There are many good EM simulators out there to help show these return paths.

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