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ADC Noise: More on the Analog Inputs

In the last two blogs, we looked at calculating the noise contribution from the driving amplifier to the total ADC noise in terms of the overall SNR (signal to noise ratio). I stepped through the calculation process using the amplifier noise, load impedance, and low frequency ADC noise. At the end of the process, we were able to see good agreement between calculated SNR and the actual SNR measured on real hardware.

It is always encouraging as an engineer to calculate expected results and see the measured results provide good correlation. Now, let's continue to look at the noise on the ADC inputs. We'll also take a quick look at noise with regards to the common mode voltage node for the analog inputs.

This time, let's take a break from the numbers game and look at some simple pointers when trying to be mindful of noise and other distortion with respect to the ADC's analog inputs and common mode voltage node. Specifically, we will look at an ADC with a switched capacitor input sampling network. Figure 1 shows a typical ADC analog input with a driver amplifier and an anti-alias filter (AAF).

Figure 1

ADC analog input network with amplifier and AAF

ADC analog input network with amplifier and AAF

The anti-alias filter is used to help prohibit noise and harmonics from aliasing back into the band of interest from other Nyquist zones in the converter. This helps reduce the overall system noise as well as filter any noise that may otherwise be coupled onto the analog inputs from somewhere else in the system. The damping capacitance, together with the series damping resistors, help to reduce the current transients that “kick back” from the ADC switched capacitor input sampling network.

These components help to provide a low impedance path for these currents to dampen out between sample clock edges. The damping capacitance can be realized in two different ways. It may be one single differential capacitor or split into two single ended capacitors. The tradeoff is based on system requirements. If system cost is of utmost importance, a single capacitor is obviously less expensive. Where it is necessary to help reduce common mode noise present in the system, the two single ended capacitors may be the best approach.

An often overlooked part of the analog input network is the common mode voltage node. In the example of Figure 1, an AC-coupled circuit is shown where the common mode voltage level of the driver amplifier and the ADC are different. This is often the case since amplifiers need higher supply voltages in order to maintain proper gain and linearity. The important thing to remember here is to route this signal away from noisy lines and use proper decoupling. Noise can find its way onto this node and enter the ADC through the VCM output or through the VCM connection into the analog input network. Also, notice that decoupling is used at the ADC as well as at the connection to the analog input network.

While we are discussing the analog input network, one last parting comment is to remember to keep symmetry in the layout of the analog input network. Any asymmetry in the analog input network will lead to an increase in the even order distortion of the ADC. This is just another form of noise resulting in decreased ADC performance. Thanks again for the comments and stay tuned at we continue to look at noise doorways in an ADC.

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5 comments on “ADC Noise: More on the Analog Inputs

  1. jkvasan
    January 23, 2014

    Jonathan,

    Nice post.

    “Any asymmetry in the analog input network will lead to an increase in the even order distortion of the ADC.”

    I am curious to know the efffect of any asymmetry introduced by the PCB layout of the analog input network.

  2. jonharris0
    January 24, 2014

    Hi Jayaraman, that is exactly the assymmetry that I was referring to.  It is very important to keep the layout of the analog inputs to the ADC as symmetric as possible.  Thanks for the comment!

  3. jkvasan
    January 24, 2014

    Jonathan Thx for the clarification. It would be great if you can discuss alternative action in case pcb symmetry in this regard if not possible.

  4. jkvasan
    January 24, 2014

    Jonathan Thx for the clarification. It would be great if you can discuss alternative action in case pcb symmetry in this regard is not possible.

  5. jonharris0
    January 24, 2014

    Hi Jayaraman, there isn't really an alternative action.  I realize that maybe I should clarify evena  bit further.  Symmetry must be maintained between the positve and negative analog inputs of each channel to the ADC.  The positive and negative of each input should be as symmetric as possible in layout. Assyemmtry will degrade even order distortion.  I was not referring to symmetry in layout between two or more channels in the ADC.  Of course, it is also good to keep symmetry between the channels but it will not affect the even order distortion of a given channel, it will just have an effect on the timing between the channels (delta would be based on the prop delay delta between the channels).  Hope this helps clarify a bit.

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