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ADC Noise: The Clock Input & Phase Noise (Jitter), Part 1

Last time, we started looking at the clock input of the ADC and how it is important to consider when looking at the overall noise of the ADC. Let's now dig a little deeper. Remember that mathematician's hat we put away a little while ago? Let's dig it out of the closet and use it to do a little math on the ADC clock input.

As most of us probably know from working in an increasingly mixed-signal world, analog and digital designers often have different ways of viewing the same problem. To one, it is po-tay-to, and to another, it is po-tah-to, or it might be to-may-to instead of to-mah-to. To the analog engineer, it is phase noise, but to the digital engineer, it is jitter. It's all in what glasses you are using to view the world and what is important in the design.

So what do we do if we are ADCs riding the fence between the analog and digital worlds? Well, we have to understand them both and how to relate them.

This is one of the few times when straddling the fence can be advantageous. Many clocking products available today specify the phase noise of the device and don't specify jitter. Let's take a look at how we can go from phase noise to jitter. We'll then be able predict the SNR of the ADC with a certain jitter. An example will have to wait, because I have only so much room here. Let's focus on the math for now. The figure below shows how we can calculate jitter from the phase noise of a clock source.

Phase noise integration over the encode bandwidth.

Phase noise integration over the encode bandwidth.

It is actually a pretty simple concept. As you can see, there are different areas under the phase noise curve that are highlighted (A1 through A5). These areas are simply the integrated phase noise power (dBc) given for each region in the datasheet for the clock source. To simplify the math somewhat, we will take a trapezoidal approximation to obtain the area in each area. To obtain the jitter from this phase noise information, we integrate the phase noise from close in to the fundamental clock frequency out to the encode bandwidth (which is the ADC sample rate).

First, we take the anti-log of all the phase noise points along the curve, and then we sum those together to achieve the integrated noise. The general idea is to take the summation of the noise across the integration bandwidth, as shown below.

This will give us the total integrated noise. Next, we need to convert this over to rms jitter in units of seconds, so we can use that to calculate the impacts on the ADC noise (SNR). To do this, we need the following equation.

We can take this data and integrate the phase noise to find the rms jitter and then derive the effects on the SNR of the ADC. As is shown in MT-008, the close-in phase noise does not have a large impact on the SNR of the ADC. The wide band phase noise has the most impact. So we can make some assumptions to make the calculations a little easier, save some time, and get a pretty good assessment on the final SNR. As we'll see later, we can pretty accurately predict the SNR of the ADC based on the rms jitter that we can derive from the phase noise of the clock source.

So now we have the tools at our disposal for calculating the rms jitter from the phase noise of a given clock source. We can now take these equations and, using the phase noise of a clock source, derive the rms jitter and find its effect on the SNR of the ADC. Next time, we'll look at an example to see how this plays out in a real-world scenario.

5 comments on “ADC Noise: The Clock Input & Phase Noise (Jitter), Part 1

  1. amrutah
    February 19, 2014

    Jonathan:

      Thanks  for the blog and super simple explaination.

    The factor of “2” in the numerator is to quantify that the noise is on both side y-axis.   The 2nd equation for tjrms, what is the factor 1/10 in the numerator for?  

  2. amrutah
    February 19, 2014

    “The wide band phase noise has the most impact..”

      So as we move towards the origin (or away from the sampling freq) the phase noise is more, meaning the rms jitter is more.  How can we quantify about the peak jitter or period jitter of the clock source.

      Can we say that the 1/f2 portion of the phase noise will help us formulate peak jitter?

  3. amrutah
    February 19, 2014

    Jonathan,

      The analogies potato and tomato is good and interesting.

      Another thing oftenly used are the FFT and EYE diagram to analyse the phase noise and Jitter respectively.

      It would be helpful if you can touch upon FFT and eye diagram co-relation. Along with the frequency domain to time domain analysis, it will also be helpful to correlate using time domain to time domain.

  4. jonharris0
    February 20, 2014

    Thanks for the great comments and questions amrutah!  To address your first question, yes the 2 is to account for each side of the fundamental tone.  The 1/10 factor is an error on my part.  When copying over equations in the equation editor I mistakenly left a /10 in the equation when it shouldn't be there.  I'll correct that in my next blog.  Thank you for spotting this and I ask you and my readers to forgive my mistake.  To address your second question…you'll see a bit more on that as we keep going, but the close-in jitter has more effect on the EVM than on the wideband noise since the Nyquist zone is >> the noise close in to the fundamental. And to your last comment, I like that idea.  I'll have to think about trying to formulate a blog around that sort of topic! 🙂

  5. jonharris0
    February 27, 2014

    The /10 error has now been corrected.  I also corrected a sign in the area equation.  Once again I apologize for the oversight on these errors.

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