ADC Noise: The Clock Input & Phase Noise, Part 3 – Test Setup

Since it has been a while since my last blog, let’s review just a bit. In the last few blogs we’ve been evaluating how to take the phase noise of a clock source and translate that into jitter ultimately arriving at the resultant SNR of an ADC. We looked at an example circuit using the AD9523 low jitter clock generator to clock the AD9643 14-bit 250 MSPS ADC. By utilizing some math we were able to determine an expected SNR value of 68.763 dBFS based on the expected phase noise performance of the AD9523 and the SNR specified in the datasheet of the AD9643. Recall that the actual measured value turned out to be 68.848 dBFS as illustrated in Figure 1 below.

Figure 1. AD9523 Clocking AD9643 at 245.76 MHz with fIN = 140.1 MHz.

Figure 1. AD9523 Clocking AD9643 at 245.76 MHz with fIN = 140.1 MHz.

As an engineer it is always rewarding when one can calculate an expected result and see the measurement in the lab line up with that calculation. One of the questions I received prompted me to decide to take a moment and give an idea of just how I came up with the plot in Figure 1.

I used the AD9643 evaluation board, which can be configured to use the AD9523 to drive the clock input of the AD9643. I don’t want to dive into the level of detail on the board configuration, but more into the basic connections. For more information on configuring the AD9643 evaluation board, please refer to the user guide. As you can see in Figure 2 we have the AD9643 evaluation board, the HSC-ADC-EVALCZ data capture board, wall power supplies, Rohde-Schwarz SMA100 signal generators, and a PC.

Once we have the AD9643 evaluation board configured, we can connect up everything as shown. We use one SMA100 to drive the analog input of the AD9643 and a second SMA100 to drive the reference input for the AD9523. These SMA100 signal generators provide us with a very low phase noise signal source, which is critical to obtain good performance from these devices. After all, we want to know the performance of the components and not the signal source driving the components. These signal generators provide low enough phase noise that it is not the major contributor in the signal chain.

The PC shown is loaded with SPIController and Visual Analog software packages from Analog Devices. The SPIController software provides an interface to the SPI port of the AD9643 and AD9523 devices so that the individual settings of the devices can be configured for the conditions we’d like to test. The Visual Analog software controls the data capture board and processes the incoming digital data from the ADC to create the FFT shown in Figure 1. It is not an incredibly complicated set up, but I thought it worthwhile to visit this to provide some more insight into how we arrived at the data that I presented previously.

Figure 2. Test Setup for Measuring SNR with AD9523 Clocking the AD9643

Figure 2. Test Setup for Measuring SNR with AD9523 Clocking the AD9643

I hope this helped to give a little more insight into the measurements I’ve been showing on the ADC that we’ve been discussing. Please keep the questions coming. We’ll continue to discuss more about ADCs. I think we have covered many of the topics surrounding broadband noise. Perhaps we’ll take time to look more at phase noise and jitter, I believe there was a good question in that regard recently. Thanks again for reading! Keep those questions coming and let’s keep having fun with ADCs!

2 comments on “ADC Noise: The Clock Input & Phase Noise, Part 3 – Test Setup

  1. Davidled
    April 19, 2014

    Firstly, it would be better to review other components with AD9523 in order to understand how SNR is affected in the test setup. Secondly, engineer might investigate Phase and Clock noise in different layer design of PCB board. For example, figure 2 shows that the number of input source is feeding into one of PCB, influencing the noise naturally.

  2. jonharris0
    April 29, 2014

    Hi DaeJ, the AD9523 phase noise will defintely be affected by the jitter of its reference source.  The point here in this blog was not to evaluate the AD9523 jitter performance but rather to look at the effect of the output jitter (phase noise) on the SNR of the AD9643.  Also, you have a very good point with the PCB.  It is always important to consider good design practices when designing PCBs such that additional noise from other sources on the PCB do not impact the noise in the ADC.  I'd recommend looking back over some of my blogs related to ADC noise for some nuggets along those lines.  Thanks for the great comments!

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