In my last few blogs, we took a pretty good look at interleaving ADCs. We have seen what advantages interleaving brings to the table as well as some of the drawbacks that come along with all that nice speed and bandwidth. Let's now move on to another topic that several readers have commented on at various points.
That question revolves around the noise contributors for an ADC. What are the things we need to consider when evaluating what the noise of the ADC will be? Noise can enter the ADC in a variety of ways. Over the next few blogs we'll take a look at all the doorways through which noise enters the ADC and can appear in an FFT of the output data. First we'll begin by identifying the doorways.
When considering noise in an ADC, one can almost consider the ADC as a mixer. If there is noise entering the ADC from any one of the various doorways, then it can manifest itself in the FFT of the output data. As Figure 1 demonstrates, noise can enter the converter through the power supply inputs, the analog inputs, and the clock.
Since noise is quite a loose term here, let's put a little more meaning to it based on which input (doorway) to the ADC is being discussed. We'll start at the top of the diagram and work our way around counter-clockwise.
The power supply inputs are pathways for noise to make its way into the ADC and appear in the FFT of the output data. In this case, there are a few ways to evaluate this noise and its impact on the ADC performance. The ADC should be designed in such a way that the device itself attenuates noise input coming from the power supply. The measurements here to evaluate noise on the power supply are the power supply rejection ratio (PSRR) and the power supply modulation ratio (PSMR). Measuring these two parameters gives us an idea of how well the ADC will handle noise entering through the power supply inputs. We'll take a more detailed look at this later. For now, let's continue looking at the noise doorways.
Next, let's take a look at the analog input of the ADC. From this perspective, noise must be considered in two ways. First, there is general broadband noise that enters the converter through the analog inputs and is generally from the components preceding the ADC in the signal chain. We can select a very low noise driver amplifier for the ADC, but there will still be a finite amount of noise that is amplified and input to the ADC.
To help combat this, an anti-alias filter (AAF) is typically used at the inputs to the ADC. This helps to filter much of the broadband noise that might enter the ADC. This ultimately shows up in the signal to noise ratio (SNR) of the ADC. In addition to broadband noise, spurious content and harmonics can also enter the ADC through the analog inputs. The AAF helps to filter these as well. This will be reflected by the spurious free dynamic range (SFDR) of the ADC. It is important to have a good AAF design to help with both of these aspects. Again, we'll look at this in more detail in later blogs.
The last doorway that we see as we move counter-clockwise around our ADC is the clock input. This input, similar to the analog inputs, can allow both broadband noise as well as spurious and harmonic content to enter the ADC and appear in the FFT of the output data. It is important to make sure an appropriate clock input driver is selected that provides a clean, low jitter input clock to the ADC.
This clock signal should be routed to the ADC in such a fashion that it does not couple in noise that can find its way into the ADC. Similar to the analog inputs, a filter may be used on the clock input to help filter out noise that may have otherwise entered the ADC through the clock input. Once again, as in the case of the analog inputs, the noise mechanisms through the clock input can manifest themselves in the SNR and the SFDR performance of the ADC.
All of these doorways must be considered when designing a system using an ADC. We see that we should treat the ADC as a mixer which mixes the various noise content from any one of these doorways onto the output data in the FFT. Obviously, a system designer would like to have the desired signal only at the output of the ADC. In order to do so, we must take the proper steps on each of these inputs to make sure that noise is minimized and does not enter these doorways. Stay tuned as we take deeper dives into each of these inputs and evaluate in more detail how noise couples into the ADC and what can be done to help prevent it.
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- Interleaving Spurs: Gain Mismatches
- Interleaving Spurs: Offset Mismatches
- More Thoughts on Interleaved ADCs
- Interleaved ADCs: The Basics
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- Signal Chain Basics #82: Crosstalk Between Outputs in Clocking Devices
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