ADCs for High Dynamic Range: Successive-Approximation or Sigma-Delta?

[Editor's note: Another ADI look into the world of electronics mystery from the series “Rarely Asked Questions: Strange but True Stories From the Call Logs of Analog Devices” guest authored by Maithil Pachchigar, a Planet Analog blogger.]

Q: I need 100-dB dynamic range for a medical imaging application. Can you help me choose between successive-approximation and sigma-delta ADC architectures?

A: High-performance data-acquisition signal chains used in industrial, instrumentation, and medical equipment require wide dynamic range and high accuracy. The dynamic range of an ADC can be increased by adding a programmable-gain amplifier or operating multiple ADCs in parallel, using digital post-processing to average the result, but these methods can be impractical due to power, space, and cost constraints. Oversampling allows an ADC to achieve high dynamic range at low cost, while also addressing tough space, thermal, and power design challenges.

Oversampling is performed by sampling the input signal at much higher rate than the Nyquist rate (twice the signal bandwidth) to increase the signal-to-noise ratio (SNR) and effective number of bits (ENOB). When the ADC is oversampled, the quantization noise is spread such that most of it occurs outside the bandwidth of interest, resulting in increased overall dynamic range at low frequencies. The noise outside the bandwidth of interest can be eliminated using digital post processing as shown in Figure 1. The oversampling ratio (OSR) is the sampling rate divided by the Nyquist rate. The improvement in dynamic range (ΔDR) due to oversampling is Δ DR = log2 (OSR) × 3 dB. For example, oversampling the ADC by a factor of four provides a 6-dB increase in dynamic range, or one additional bit of resolution.

Figure 1

Oversampling of Nyquist ADC

Oversampling of Nyquist ADC

Oversampling is inherently implemented in most sigma-delta (Σ- Δ) ADCs with integrated digital filters, where the modulator clock rate is typically 32 to 256 times the signal bandwidth, but Σ- Δ ADCs are limited for applications that require fast switching between input channels. The SAR architecture has no latency or pipeline delays, enabling high-speed control loops and fast switching between input channels, and its high throughput rate allows oversampling.

Although both ADC topologies can accurately measure low-frequency signals, the power consumption of a SAR ADC scales with throughput rate, reducing power consumption by at least 50% as compared to Σ- Δ ADCs, which typically consume a fixed amount of power. ADI's AD7960 5-MSPS, 18-bit SAR ADC provides an example of high throughput rate with linear power scaling.

The low-pass filter placed in front of a SAR ADC minimizes aliasing and reduces noise by limiting bandwidth. The high oversampling ratio and digital filter of Σ- Δ ADCs minimize the anti-aliasing requirements at their analog inputs, and oversampling reduces the overall noise. For added flexibility, custom digital filtering can also be performed on the FPGA.

The low noise floor and high linearity of high-performance SAR ADCs allow them to provide increased bandwidth, high accuracy, and discrete sampling in a small time window required for fast measurement and control applications. Their high throughput rate, low power, and small size helps designers meet space, thermal, power, and other key design challenges common to high-channel-density systems. SAR ADCs also offer the lowest noise floor relative to the full-scale input signal, resulting in a higher SNR and excellent linearity, but unlike Σ- Δ ADCs they cannot reject 1/f noise close to dc (50/60 Hz).

SAR and Σ- Δ ADCs each have their own pros and cons. The data-acquisition system designer must make tradeoffs based on performance, speed, space, power, and cost requirements.


13 comments on “ADCs for High Dynamic Range: Successive-Approximation or Sigma-Delta?

  1. vasanjk
    August 28, 2014



    The post provides a bird's eye viewpoint on the pros and cons of both techniques while providing an informed freedom to the reader to easily choose between the two.


    I am curious to know how an oversampled SAR ADC fares against the two. I have myself used oversampling with a 10 bit ADC to achieve a 12 bit resolution for a non critical application.

  2. Maithil Pachchigar
    August 28, 2014

    Analog Devices app note AN-1279 explains in detail how you can oversample the SAR ADC and achieve the increased the dynamic range.

  3. chirshadblog
    August 29, 2014

    @Maithil: Thank you for the info. I was curious about it because I had a different idea about it. 

  4. vasanjk
    August 29, 2014



    I have read this app note and a similar one published by SilabS and I implemented it in a Renesas MCU design with good results.


    My question is between a 12 bit ADC and an oversampled 10 bit ADC, how could one decide based on the pros of both?

  5. Maithil Pachchigar
    August 29, 2014

    You would need to consider tradeoffs between 10-bit and 12-bit ADCs based on performance, space, power, and cost requirements.

  6. geek
    August 29, 2014

    @Maithil: I think it also depends on the nature of application. For an R&D experiment in the lab, performance would be the key priority because that can't be compromised on. For a production environment, cost would be more important because the quantity would need to be procured in a bulk quantity.

  7. samicksha
    August 29, 2014

    I guess the key here is conversion time, conversion time is very short. When we consider10-bit ADC with a clock frequency of 1 MHz, the conversion time will be 10 microseconds.

  8. vasanjk
    August 30, 2014



    A single conversion time may not be important. During oversampling, several samples are taken and data manipulated. This “no of samplesX conversion time” could impact the overall data thoroughput.

  9. vasanjk
    August 30, 2014



    Nowadays so much of information is available that helps in deciding on peripherals early in the design life cycle. Normal practice would be to freeze ADC specs at the design stage itself. The decision between selecting a 12bit ADC and a 10 bit software oversampled ADC is taken probably at the start itself.

  10. Victor Lorenzo
    August 30, 2014

    The ADC architecture and its digital interface determine the convertion time, or better said, the time it takes for having the sample stored in the CPU memory and ready for processing.

    SAR ADCs can exhibit a longer “effective” convertion time when interfaced using SPI or multiplexed data bus than with a full word sized parallel data bus (considering the same conversion clock speed).


  11. Davidled
    September 1, 2014

    It could be depending on application between data converter and other device used in the application. ADC latency could be measured in the clock cycle. Each latency could be considered from analog front end to digital output with propagation delay (Tpd) measuring the delay on clock input and on clock output and data. Also, with overall system latency review, ADC resolution could be selected by designer.

  12. samicksha
    September 11, 2014

    I understand your but i just tried taking reference, although i accept that oversampling is process of sampling the input signals at much higher rate.

  13. Davidled
    September 14, 2014

    Oversampling might be not a solution for this case. Solution might need multiple signal conversion stages such as filtering to get the right frequency signal. Incorrect ADC process might produce unwanted interleaving artifacts, causing misinterprets the original input signal. I am wondering if there is a method to get the ADC, related to post processing.

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