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ADCs with quadrature error correction slowly replace IF architectures

Traditional communication equipment, such as basestations and mobile phones, use an intermediate frequency (IF) sampling architecture to support various air interfaces. However, there are a growing number of designers wishing to build direct conversion systems, according to Analog Devices' Jon Hall, strategic marketing and applications manager for high speed converter products. And customers for ADI's direct conversion products apparently include those involved in traditional communication systems design.

One of the ways in which Analog Devices is expanding its data converter product line is by combining low power filtering upstream of the ADC, in the form of quadrature error correction (QEC). QEC dynamically addresses the errors produced in an in-phase/quadrature (I/Q) complex signal receiver system, allowing system designers to relax component matching requirements by reducing gain and phase errors due to component mismatches. Implemented on-chip as an option in the AD9269, QEC minimises design time, cost and footprint overhead for users, and can offload the processing requirements on an FPGA.

The QEC concept isn't new. ADI offers two discrete digital down converters with its AD8376 and AD8366 VGAs, and last year it launched a continuous time sigma delta dual 16bit ADC with QEC – the AD9262. However, the introduction of the AD9269 family is the first time this feature has been integrated in a low power dual-channel 16bit ADC, says Hall, and thus it marks a shift in expectations about where direct conversion can be used.

Observes Hall: “Your handset, WiFi or WiMAX customer premise equipment, are typically direct conversion based receivers, but as you work your way towards a microcell or a macrocell, that requirement switches over to IF sampling due to the performance requirements in a macrocell and the number of air interfaces that an OEM wants to support. In five years, we'll be talking direct conversion for everything, but right now, this represents an evolution to direct conversion.”

The AD9269 is one of 26 high speed ADCs just launched by ADI. Consuming just 93mW per channel at its highest sampling rate, it comes in 20, 40, 65 or 80MS/s variants. Common to each is the on-chip voltage reference and sample-and-hold circuit, plus of course, the QEC and a DC offset digital processing block.

Among ADI's latest ADC offering are the AD9265, a single-channel 16bit low power ADC with 80 to 125MS/s, and the AD9266 – reputedly the industry's smallest single-channel 16bit low power ADC with 20 to 80MS/s. To improve and encourage the process of product migration up the ADC chain by customers, ADI has provided each of these families with the same pin orientation.

Samples of the AD9269 and the AD9266 are immediately available, with production quantities starting in January, 2010. Production quantities of the AD9265 are available already.

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