As the market for cost reduction increases in intensity, the pressure is mounting to integrate or embed more of the functions within complex integrated circuits. The constant need to embed more of the electronic systems to reduce the bill of material costs and improve performance is driving the need to embed more complex analog functions within these integrated circuits. In particular, the analog-to-digital front end of these embedded systems is seeing an increasing trend toward improving sensitivity and performance. Likewise, there is the push to integrate more of these types of analog ADC front ends while reducing power and area.
The use of ADCs within integrated ICs has been around for many years. However, the integration of high-performance ADCs with microvolt sensitivities and adequate isolation to achieve targeted performance parameters, which are relatively constant and do not vary in time, is a challenge for integrated ASICs. This is especially true when the target ICs for these integrated ADCs have large memories and processing cores.
The problem with conventional Nyquist rate switch capacitor and discrete time switch to capacitor Sigma Delta ADCs is that sampling occurs at the first stage, where any unwanted energy can easily be sampled on to the input capacitance and as a result fold back into the bandwidth of interest. This folding of undesired energy within the bandwidth of interest may destroy the sample and result in degraded SNR performance.
Shown in Figure 1 is a simple stage as would be found in a typical Nyquist and discrete time Sigma Delta ADC. As shown in that figure, unwanted energy near the sampling frequency is folded and can fall in the band and destroy the SNR. In addition, unwanted energy close to the sampling instant can destroy the sample and reduce the SNR.
Because of the phenomenon of folding, the trend for embedded ADCs is to move to a continuous time ADC function. Shown in Figure 2 is a generic continuous time Sigma Delta architecture. As can be seen in the architecture, the sampling function occurs in the quantization block (most often some type of flash ADC) after the gain of the integrators in front of the quantizer.
Because the sampling function occurs inside the loop, any unwanted energy that is sampled and folded is suppressed by the loop gain (or the gain of the integrators in the forward path). For Sigma Delta converters of the continuous time nature, the sample folded energy is suppressed and shaped out of the bandwidth of interest. Therefore, these types of converters are ideal for use within embedded systems, where the frequencies and energy of the unwanted signals are generally asynchronous to the sampling clock of the ADC and often uncontrolled in magnitude.
Furthermore, the continuous time Sigma Delta converters in general do not draw as much power or create as much noise as the discrete time equivalent circuits for the same effective number of bits. The benefits just mentioned for using continuous time conversion, along with the situation inside an IC that the magnitude of the unwanted energy that appears at this Sigma Delta front end is often dependent on the amount of isolation achieved, provides further weight to the need for these type of converters within embedded systems.
Remember that the isolation achieved within the IC depends on the package, IC layout, block placement of the ADC within the IC, package type, inductance, etc. These various factors that affect the performance of embedded circuits create challenges for the integration of these circuit functions. However, by using continuous time Sigma Delta ADCs for the front end, the effect of these various factors that can significantly degrade performance is reduced. This reduction in sensitivity to the integration of the ADC function can make the difference between failure and success for the embedded system.
Let me know what you think. Do you agree with these statements? Do you have any experience where using a discrete time ADC integrated within a complex IC did not work as expected due to inadequate isolation? Or unwanted clock energy at the sampling instant?