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ADPCM Processor – has eight full-duplex channels

An eight full-duplex channel, ADPCM processor which follows the G.726 ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable µ-law and A-law input/output, the Atelic AT1008F chip from Steadlands can operate on 16 channels of PCM to ADPCM compression, 16 channels of ADPCM to PCM decompression, 8 channels of full-duplex operation in an 8KHz frame basis, or any combination of M-channels of compression plus N-channels of decompression when M+N is less than or equal to 16.

Through its three wire serial port, the AT1008F can be dynamically programmed to perform the ADPCM algorithm at different bit rates, idle or reset the algorithm. It can also be programmed to set up different input/output time bit-slots, or to select (a) bypass without compression at 64kbps PCM, (b) idle, or (c) reset the algorithm.

Available in either 28-pin DIP or SOP packages and designed for T1/E1 applications, the component has two clock pins (CLKA and CLKP) used as PCM/ADPCM data clocks and the two pins (FSX and FSY) used for the two Frame Sync signals can be programmed either as input or as output pins.

Steadlands International Marketing Ltd , Blyth, Northumberland NE24 3YE, UK.
www.steadlands.com

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