Advances in architecture and integrated-circuit (IC) design techniques have allowed analog-to-digital converter (ADC) manufacturers to push the state-of-the-art in sample-rate, resolution, and power. In so doing, ADC designers have simplified development of many systems while enabling the next generation of others. For instance, simultaneous improvements in sample rate and resolution of ADCs simplify the design of multi-carrier, multi-standard software defined radios.
These radios must digitize a wide frequency spectrum with high dynamic range to simultaneously receive near and far transmitters using multiple signal formats.
Similarly, advanced radars require increases in ADC sample rate and resolution to improve their sensitivity and accuracy. While the improvements in ADC performance enable specific features of many applications, all systems benefit from the order-of-magnitude improvements in power consumption of the ADC through simpler system thermal design and more compact physical design.
In communications applications, using a single ADC to digitize entire spectral bands, rather than a limited number of channels, can simplify receiver design. In order to achieve this, the entire spectral band must fit within a single Nyquist zone of the ADC, meaning the sample rate (Fs) must be at least two times the spectral bandwidth (BW) of interest (Fs ≥ 2 × BW). However, a significantly higher sample rate simplifies the necessary anti-aliasing filters and the preceding stages in the receiver.
For example, it is possible to digitize the entire 75 MHz GSM band using a sample rate of 184.32 MSPS with highly selective filters. Limiting the filter to third-order requires ADC drivers with second harmonic distortion (H2) better than -75 dBc. As illustrated in Figure 1 , the distance from the band edge to the first interfering harmonic that will alias back in band is only 25.74 MHz
Figure 1. H2 image separation for Fs = 184.32 MSPS .
Increasing the sample rate to 491.52 MSPS as shown in Figure 2 moves the closest alias image 140.04 MHz away from the band edge, relaxing the combined filter-plus-driver requirements.
Figure 2. H2 image separation for Fs = 491.52 MSPS .
Figure 3 illustrates the frequency response of two hypothetical 3rd -order hourglass filters. For the case of 491.52 MSPS, the increase of 114 MHz in the distance from interferer to band edge allows the filter to generate much larger stop-band attenuation. This allows the use of a lower power ADC driver with 23.5 dB less second-harmonic performance.
Figure 3. Frequency response of two 3rd order hourglass filters.
Furthermore, oversampling the spectral band of interest allows more flexible frequency planning for radio designs. In many cases, oversampling will make it possible to position the aliased second and/or third harmonics out of the band of interest. This capability enables a given 14-bit, 500 MSPS ADC’s already-excellent high-frequency spur-free dynamic range (SFDR) performance to improve by another 8 dB over a 55 MHz bandwidth centered at 194.5 MHz.
A high-resolution ADC capable of sampling at 491.52 MSPS would allow a 75 MHz band of interest, centered on 122.88 MHz, to be free of all aliased second harmonics, as illustrated in Figure 4 . Because none of the second harmonics of the 75 MHz band alias into the band of interest, they can be easily filtered in the digital domain. This further eases the filter and ADC driver requirements, reducing radio cost and complexity.
Figure 4. Frequency plan for a 75 MHz receiver at 491.52 MSPS
An additional benefit of oversampling is an improvement in the noise floor in the desired channel. This can be understood by looking at the noise in “per Hz” units, instead of the typical Nyquist bandwidth singal-to-noise ratio (SNR). The equation:
SNR [dBFS/Hz] = SNR [dBFS/Nyquist] + 10 × log10 (Fs/2)
(note: dBFS is dB full scale) translates between these two. For the same 491.52 MSPS rate used above, an ADC that provides a Nyquist SNR of 73 dBFS (full scale) offers SNR/Hz of 156.9 dBFS/Hz. The output noise of an ADC with the same Nyquist SNR sampling at 184.32 MSPS is only 152.6 dBFS/Hz. The increased sample rate provides an SNR improvement of 4.3 dB for channel widths less than the Nyquist frequency of the lower-sample-rate converter.
Alternatively, the SNR improvement due to oversampling can be calculated as:
10 × log10 (Fs1/Fs2).
For Fs1=491.52 MSPS and Fs2=184.32 MSPS, the improvement is the same 4.3 dB.
As in many communications applications, the defense-electronics industry has been trending toward receivers with more bandwidth and higher dynamic range. Applications in this segment include Signals Intelligence (SIGINT) receivers, as well as radar for military and Homeland Security usage. SIGINT systems can be classified as Communications Intelligence (COMINT, communication between people) or Electronic Intelligence (ELINT, typically radar signals).
Both COMINT and ELINT systems benefit from higher bandwidth, since more information is gathered in a given amount of time. Higher bandwidth in a radar receiver produces greater spatial resolution, which in turn creates the ability to distinguish smaller targets or multiple targets that are clustered together.
Traditionally, 100-200 MSPS high-resolution ADCs have been used in SIGINT and radar receivers. More recently, these systems have employed 12-14 bit converters with sample rates in the 250-500 MSPS range. Current developments are requiring multi-GSPS converters in this same resolution range, which favors time interleaving of multiple monolithic ADCs on the printed circuit board. In this application, the power consumption of each ADC is critical, since some radar receivers may use hundreds of ADCs.
A second trend in defense electronics receivers is toward higher dynamic range, which is predominantly set by the SNR. Dynamic range defines the receiver’s ability to detect small signals in the presence of large signals.
For example, consider two objects being imaged by a radar system in which the target is further from the antenna than a second object. The closest object will produce the strongest backscatter signal, thereby determining the total gain that can be applied without saturating the receiver. The target signal will be much smaller, and may not be received at all if its magnitude is below the detection threshold set by the dynamic range.
In SIGINT systems, higher dynamic range translates to successful capture and decoding of weaker or more distant signals in the presence of interference (either natural or man-made), thereby providing more advanced warning of threats. A low power, high SNR, 14-bit, 500 MSPS ADC, such as the ISLA214P50IRZ from Intersil — with built-in support for time-interleaved systems — is an enabling technology for the defense electronics industry, especially SIGINT and radar.
As ADCs meet the dynamic range and sample rates described earlier, power consumption in such devices becomes important. Prior generations of ADCs, while having lower sample rates and less dynamic range, consume several watts of power.
This level of power consumption has implications for system performance, beyond obvious areas such as electricity cost and battery life. Dealing with the heat generated by an ADC dissipating multiple watts can create limitations in many applications. Beyond simply managing the heat, the elevated temperature creates performance and reliability issues not only for the data converters, but also all of the surrounding components and circuitry. Because of these issues, finding an ADC that can meet the performance targets described that also consumes under 1 W of power relieves additional design constraints.
One obvious implication of very high power consumption is simply energy use. For applications that require the roll-out of tens of thousands of elements, every milliwatt consumed in the unit-element counts. For instance, savings of 1.5 W per element in a network of 36,000 4G basestations, would amount to a 50 kW power savings to the operator.
Furthermore, while technology dedicated to infrastructure is not typically thought of as battery-powered, these systems often do require a battery back-up. Lowering system power consumption reduces the requirements and costs of battery back-up.
A further complication of high power consumption is the heat generated by these devices. This is an especially important consideration in small enclosures and array applications that have limitations on the element spacing. In many telecom applications, the electronic circuit boards are designed to be rack mounted with approximately 1” (2.5 cm) vertical spacing from board to board.
In this configuration, the heat sinks typically required for multi-watt consuming devices are difficult to accommodate. Furthermore, in applications such as phased-array radars where the element spacing is a function of the microwave signal wavelength, the thermal density becomes very high.
Assuming the thermal constraints of a system’s enclosure can be managed, the performance and reliability degradation created by consistently high operating temperatures must be analyzed. In the case of a typical IC with a thermal resistance (ΘJA ) of 20-50°C/W and consuming 2.5 W, the junction temperature can be as high as 50-125 °C above the ambient temperature, without adequate heat-sinking. Since thermal noise is proportional to the square root of temperature, any increase in the junction temperature of the ADC will negatively impact its SNR.
This can be significant. For instance, a 60°C increase over room temperature (27°C) will produce a roughly 10% increase in thermal noise, which could translate to approximately a 1 dB decrease in an ADC's typical SNR.
Furthermore, expected device lifetime is inversely proportional temperature. For a typical IC, every 40°C increase in junction temperature can decrease expected device lifetime by a factor of two to three times. This presents a serious challenge for applications that are expected to have long field lifetimes.
Clearly, the advances of the ADC translate into numerous benefits for a wide variety of applications. For example, a 14-bit, 500 MSPS ADC consumes less than 1 W of DC power. This allows a base-station receiver to digitize the entire 75 MHz GSM band and use a low-power ADC driver and simple channel filtering, while avoiding the need for high-current LDOs and bulky heat sinks and fans.
Similarly, the same ADC would allow advances in state-of-the-art phased-array radar design. Its very-high sample rate and resolution allow improved sensitivity, while the decrease in power consumption allow simplified thermal design, especially where the element spacing is constrained to be small. Thus, improvements in ADC technology are enabling advancement in performance, reliability, and cost of systems that are dependent upon them
Intersil understands the challenges facing designers of high performance systems and is introducing a family of converters that meet the demanding requirements of these applications. The first ADC of the family, the ISLA214P50IRZ, is a 14-bit, 500 MSPS ADC that consumes 925 mW of power and provides over 73 dB of SNR. Due to its combination of very-high sample rate, very-high dynamic range, and ultra-low power, this converter is well-suited for applications such as broadband communications, radar and satellite antenna array processing, high-performance data acquisition, power amplifier linearization, and communications test equipment.
About the authors
Edward Kohler is Senior Strategic Marketing Manager for High Speed Data Converters at Intersil Corporation and has worked in high-speed ADC design and marketing for eight years. He earned his BSEE degree from Michigan Technological University, his MSEE degree from the University of Michigan, and his MBA degree from Yale University.
Mark Rives is a Principal Applications Engineer supporting High Speed Data Converters at Intersil Corporation. He worked on a wide range of IC designs before moving into applications over 10 years ago, where he has focused on high-speed ADCs, DACs and communications systems. Mark received a BSEE from Mississippi State University.
Dave Carr is Applications Manager for Data Conversion products at Intersil Corporation, and has been involved in high-speed ADC and DAC development activities for 15 years. He received his BSEE and MSEE degrees from Binghamton University.