Last month, one of the top global reverse engineering chip firms, Chipworks, verified the Core M version of Intel’s Broadwell processor, using 14nm node size logic processor semiconductor technology, implemented in its first commercial product, Lenovo’s Yoga 3 Pro laptop. Chipworks was able to remove and dissect the processor chip for cross-sectional scanning electron imaging that confirmed this node size shrink from 22nm technology, with slightly modified fins for the 3D gates that started a paradigm shift across the industry several years ago. Now all top processor chip-makers such as Samsung, Global Foundries, and TSMC utilize some form of a 3D FinFET, which boosts speed and reduces power consumption.
Intel and IBM will be presenting a review of this technology at the IEDM Conference in December, which will possibly disclose the innovative use of speculated air gap interconnect insulation in the backend dielectric stack. Intel's paper will be called “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size,” which is a mouthful.
While at Micron, which was the first company in the semiconductor industry to implement double-patterning for advanced commercial chips, I was involved in pioneering this technology that has paved the way for chip scaling, amid the continued delays in direct patterning using extreme ultraviolet photolithography (EUV). I coauthored a number of patent publications including: US 8,129,289 B2 and US 8,852,851 B2. Chipworks confirmed the SRAM cell size in the cache memory is ~0.058 µm2, as well as a 42nm transistor fin pitch, 70nm transistor gate pitch, and a 52nm interconnect pitch, which are all significant scaling reductions from Intel’s prior generation processors.
Intel has been manufacturing FinFETs in high-volume since 2011, starting with its 22nm Ivy Bridge and later Haswell processors, using a more traditional silicon scaling approach. In contrast, IBM is using higher cost silicon-on-insulator (SOI) substrates to streamline the manufacturing process, enabling lower-voltage operation and subsequently lower-power chips, which are super-critical for mobile device applications.
However, IBM has subsequently sold its chip enterprise to Global Foundries, which will be carrying the torch on this technology moving forward. FinFETs were designed to reduce current leakage in newer generation, smaller gate transistors, which do not require SOI substrates. In FinFETs, the gate wraps around the fin channel, so it is possible to deplete the channel in the off-state, reducing leakage current that can overheat and degrade the processor chips.
Beside integrated device manufacturers (IDMs), foundries across the world are shrinking chip node sizes for next-generation electronic devices. According to a recent report by IC Insights, TSMC is forecast to have the highest revenue per wafer in 2014, at $1,328, which is 27% higher than Global Foundries and 42% higher than UMC. There is a definite trend between revenue and node size in the results. The most profitable node sizes tend to fall below 28nm scale chips. The pure-play foundry sales are predicted to reach $12.3 billion in 2014, equivalent to a 72% spike from 2013. The market size for devices below the 28nm node size still represents the largest segment of the market at 71%, but it is only expected to increase 4% this year.
The growth in shrinking chip feature sizes is partly due to the expansion of the high-performance wearable electronics market, including smartwatches and smart headphones. Market research forecasts across the industry are predicting growth of nearly $60 billion for the wearable electronics market over the next decade. Since Apple has not even penetrated (or shaken up) this space yet with its iWatch, which has been delayed until the spring of 2015, it is possible that these forecasts may even be underestimates if Apple's first such product is a smash hit.