Below 28 nm, maximum device length limitations mean that analog designers often need to connect multiple short-length MOSFETs in series to create long-channel devices. These series-connected devices are often called stacked MOSFETs or stacked devices. For example, stacking three 1-um MOSFETs in series creates an effective device with a channel length of 3 um (Figure 1).
Figure 1 Three MOSFETs are stacked in series to offer a channel length of 3 um. Source: Pulsic
Stacked MOSFETs are very common in modern analog design but are not without issues. The main problems are increased capacitance and greater area. The increased capacitance is largely due to the increase in interconnect around the devices. The overall gate area and gate capacitance remain similar to the non-stacked equivalent, but there is extra parasitic capacitance on the interconnect. The physical separation of the devices in the stack increases the overall design area compared to a single long-channel device.
When using stacked MOSFETs in a circuit, the layout quality becomes even more critical than usual. Poor layout increases the parasitic capacitance and design area significantly and can result in a circuit failing to meet the desired performance characteristics. So, engineers must design the layout of such devices with great care. Most designers working at these smaller process nodes have experienced situations where pre- and post-layout simulations are very different. Quite often, this is due to the effects of interconnect parasitics on stacked devices.
Let’s take a look at a few ways of achieving a high-quality layout for stacked MOSFETs. The sub-circuit below shows four NMOS MOSFETs that have been stacked together to create a long-channel device (Figure 2).
Figure 2 Four MOSFETs are stacked to create a long-channel circuit. Source: Pulsic
In this circuit, you can see that all the gate pins are connected—as are all four bulk connections—and you can also see that the MOSFETs have been connected in series with the drain of one connected to the source of the next. Because, in this case, each device is a simple single-finger MOSFET, so we can use a simple diffusion-sharing layout pattern when designing a layout for this structure.
Figure 3 The simple stacked case on the left is compared to the equivalent long-channel device on the right. Source: Pulsic
The layout of the simple stacked case is shown on the left of Figure 3 above; you can see that there is very little additional interconnect, as the equivalent long-channel device (on the right) would also require a poly contact. The area penalty is significant in this case, but this is unavoidable and determined by the poly min-spacing rule.
Another problem with this approach is that very long effective devices can result in long chains of diffusion sharing. However, it’s possible to fold long chains onto multiple rows, as shown in Figure 4 below. The tradeoff is that this adds additional interconnect and further increases the capacitance of the stacked device.
Figure 4 Long chains are folded onto multiple rows. Source: Pulsic
The following circuit shows a case where the circuit designer wanted to use two-finger MOSFETs in the circuit to achieve better matching (Figure 5).
Figure 5 The circuit uses two-finger MOSFETs to accomplish better matching. Source: Pulsic
Two-finger devices cannot be connected by diffusion sharing, so we must use a different placement and routing approach. In order to achieve a compact layout, the devices are connected in columns instead of the row-based pattern shown in the previous example.
Figure 6 The connectivity runs in columns (left) and the routing mechanism for this column-based pattern is shown on the right. Source: Pulsic
In Figure 6, the image on the left shows the connection pattern, the drain of one device connecting vertically to the source of the next. As you can see, the connectivity runs in columns, with alternating devices having different parameters that swap between the drain-center and the source-center variants of the MOSFET. The swapped contacts allow straight-line routing between the devices in the column, avoiding bends and additional vias.
You can see the routing mechanism for this column-based pattern on the right. There is additional interconnect, but not significantly more than would typically be needed anyway for contact reinforcement.
The circuit designer might also specify an m-factor for the stacked device. A stacked and m-factored topology allows the circuit designer to build devices with long and wide channels using a number of small MOSFETS. Figure 7 shows a single-finger stacked device with an m-factor of 4.
Figure 7 A single-finger stacked device is shown with an m-factored topology. Source: Pulsic
The blog has shown a few of the basic patterns that can be used with stacked MOSFETs. In all of these examples, the placement and routing of the devices are critical in achieving a high-quality layout.
The technology in Pulsic’s Animate Preview tool combines placement and routing in a single operation. This allows Animate Preview to achieve the type of optimal layout pattern for stacked devices shown above. The exact position, orientation, and parameterization of each device must be optimized to obtain the desired result. At the same time, the tool must consider the current flow through each device, so that the interconnect complexity and length are minimized. Analog layout always requires a careful balance of multiple competing priorities; no one way of doing things will work in all cases.
After starting his EDA career as a software engineer at Zuken Redac in 1996, Mark Waller co-founded Pulsic in 2000 and served as VP of R&D for over 15 years. Following a career break as a high school physics teacher, Waller is now back at Pulsic and leads user enablement for Pulsic’s Animate product line.
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