Altera expands transceiver based FPGA range

LONDON — Altera is expanding its transceiver based range of FPGAs, both of which will be made by TSMC in a 40-nm process and which extends the range of parts from 175Mbits/s to 11.3Gbits/s.

The Stratix IV GT and Arria II GX parts will join two other families, the Stratix IV GX FPGAs and HardCopy IV GX ASICs that are already shipping.

All four ranges use the same common transceiver technology and are supported by a common set of development tools that enable system designers to develop full system-on-chip (SoC) solutions.

“Transceiver based FPGAs are growing at a tremendous pace at the moment, driven by the need to compress and transmit ever more amount of data and video,” said Luanne Schirrmeister, senior director for low-cost product marketing at Altera (San Jose, Calif.).

And while communications infrastructure is the main application target of the new ranges, “that is definitely not the end of the story. These will find applications in industrial Ethernet, consumer, automotive and medical applications as well.”

The devices offer excellent signal integrity, the lowest jitter specifications, and broad high-speed I/O protocol compliance, she adds.

The Arria II GX devices are said to be the lowest power 3.75 Gbits/s transceiver FPGAs made available, and are optimized for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE). They feature up to 16 3.75-Gbits/s transceivers, 256K LEs, and 8.5 Mbits of internal RAM.

The parts support targeted protocols such as CPRI for LTE and WiMAX wireless infrastructure access equipment, GPON and XAUI for wireline infrastructure access and networking equipment, and triple-speed SDI for broadcast and other video processing equipment.

The first Arria II GX device, the EP2AGX125, will ship in May 2009 with production devices scheduled for the fourth quarter of 2009.

The Stratix IV GT devices are said to be the industry's first FPGAs to include integrated transceivers operating at 11.3 Gbits/s, and the architecture is optimized for 40G and 100G applications such as communications systems, high-end test equipment, and military communications systems. The parts have 24 transceivers operating at 11.3 Gbits/s, and an additional 24 transceivers operating at 6.5 Gbits/s.

They also offer up to 530K LEs, 20.3-Mbits internal RAM and 1,288 18 x 18 multipliers, and have just started shipping.

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