Blog Signal Chain Basics

Amplify small signals in low-noise circuit with discrete JFET

Amplifying the small signals produced by sensors in a low-noise circuit is a very common but difficult problem. Designers will often use an operational amplifier (op amp) with bipolar inputs to achieve this amplification, given their inherently low flicker (1/f) and broadband noise. Bipolar op amps present another challenge when the small signal of interest is generated by a sensor with high source impedance that cannot deliver sufficient current to the amplifier’s input. Bipolar op amps have high input bias currents in the nanoampere range or greater, and lower input impedance relative to their CMOS- and junction field-effect transistor (JFET)-input counterparts.

The bipolar input will load a sensor such as a high-source-impedance microphone that produces signals on the order of a few thousandths of a volt. This loading will reduce audio sonic quality and dynamic range and distort the signal. You could choose an op amp with a JFET front-end such as the OPA145 from Texas Instruments; however, you will not be able to bias the circuit as flexibly as you could with discrete components, and you may sacrifice extra current for unwanted bandwidth relative to the bandwidth of audio signals of up to 20 kHz.

While CMOS and JFET input stages have comparable bias currents, JFET devices have much better noise performance. Moreover, JFETs have higher gain (transconductance) than CMOS devices. A discrete JFET such as TI’s JFE150, when followed by a bipolar op amp such as the OPA202, does offer a way to achieve high input impedance and low noise with flexible biasing (Figure 1).

Figure 1 The JFET pre-amplifier closed-loop circuit facilitates low noise with flexible biasing. Source: Texas Instruments

To understand the operation of this circuit, let’s start by examining it at the input. A sensor will generate a small-signal input voltage (vin), which modulates the gate-to-source voltage (vgs) of the JFET. The JFE150 is the first gain stage in the pre-amplifier circuit and conducts a small-signal drain-to-source current, ids = gm × vgs which fluctuates with vin. The small signal current, ids, is not to be confused with the DC bias current, IDS = 2 mA, as shown in Figure 1. The transconductance gain parameter (gm) is expressed in Siemens and vgs is expressed in volts.

Combined with resistor R1, the OPA202 op amp forms a transimpedance amplifier that converts the current gm × vgs to a voltage, vout. The OPA202 op amp will drive the loop in order to keep its input terminals approximately equal. As a result, most of the current gm × vgs will flow through resistor R1 in the mid-band frequencies, producing an amplified voltage at vout. Equation 1 calculates the feed-forward gain (Av):

Av ≈ gm × R1 (V/V)               (1)

You can convert gm from decibels to Siemens (mA/V) or Ω-1, as shown in Equation 2, using the simulated measurement from Figure 2.

gm = 10 -36.08dB/20dB = 15.7 mS            (2)

Figure 2 A gm (dB) vs. frequency (Hz) plot is used to convert decibels to Siemens. Source: Texas Instruments

Equation 3 and Equation 4 show that the feed-forward gain is:

Av = 15.7 mS × 1 MΩ = 15.7 kV/V                 (3)

AdB = 83.92 dB                  (4)

Because wafer process variations can yield up to 30% variations in gm, adding a feedback network (β) will maintain a predictable closed-loop gain. The feedback network β consists of resistors RF2, RS1 and RS2 and capacitor Cs, and is a series-shunt feedback network. The β network samples vout by shunting the output of the OPA202 and feeds back a proportional voltage vfb in series with vgs. At frequency, Cs becomes a short, and Equation 5 and Equation 6 express the small-signal gain as approximately:

Acl ≈ RF/RS2 + 1       (5)

Acl ≈ 1001 V/V or 60 dB       (6)

The source node of the JFET is the feedback-summing node of the circuit. In this configuration, the loop is closed. If vout rises, then vfb rises. An increase of vfb at the source node decreases vgs, resulting in a reduction of current gm × vgs that flows through transimpedance resistor R1. The final outcome is a reduction of vout which completes the negative feedback loop of the pre-amplifier. Figure 3 shows the closed-loop gain vs. frequency response of the JFET pre-amplifier circuit.

Figure 3 Closed-loop gain (dB) vs. frequency (Hz) response is shown for the JFET pre-amplifier circuit. Source: Texas Instruments

The JFE150 pre-amplifier circuit provides very high gain at 60 dB and a flat frequency response from approximately 17 Hz up to 43 kHz. The clean roll-off at the corner frequencies provides a natural-sounding filter for audio signals without sounding abrupt at the low and high ends. This closed-loop solution also offers very low input-referred noise of 1.99 nV/√Hz in the 1/f region at 10 Hz and 1.18 nV/√Hz in the broadband region at 1 kHz, as shown in Figure 4. Make sure to provide a clean power supply to this circuit in order to not degrade its remarkable performance.

Figure 4 The input-referred voltage noise density  vs. frequency curve underscores a closed-loop solution. Source: Texas Instruments

Amplification of small signals in applications such as professional microphones, audio interfaces, mixers, turntables and guitar amplifiers is very challenging. These types of applications can benefit from the bias flexibility, high input impedance, and low noise that a discrete JFET offers.

Chris Featherstone, author of Signal Chain Basics blog # 169 for Planet Analog, is applications engineer at Texas Instruments (TI).

Related Content

2 comments on “Amplify small signals in low-noise circuit with discrete JFET

  1. Andrew Mackay
    September 5, 2021

    Wow this design is full of school boy errors designed to mismatch source and load impedances = 0 putting large value capacitors on input pins direvtly is not recommended even on three terminal voltage regulators without including a power off discharge path and a bias resistance.

    • Chris Featherstone
      September 8, 2021


      The input impedance is intentionally meant to be very high in order to accomodate high impedance sources. The purpose is to not load the sensor generating the input signal. The input capacitor in this article is 10uF, however I have tested this circuit with 100uF caps. The low corner frequency formed by Cg and Rg can be adjusted to form the high pass filter between the input and the gate of the JFET as desired. Rg can be adjusted as desired. It’s purpose is to bias the gate to 0V to run the JFET at IDSS.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.