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An Isolated Potentiometer: The Analog-Actuated Potentiometer, Part 2

In the previous part of this article An Isolated Potentiometer, Part 1, the current sources used in the isopot – both Howland and op-amp V/I – were explained. We now get to the heart of the isopot circuits: the multipliers. The two multipliers comprise the LM13700 dual translinear amplifier. Detailed design derivations and application now proceed, followed by prototype build and testing. The isopot circuit diagram is repeated at the end of this second part of the article.

LM13700 Translinear Amplifier

The simplified circuit diagram of the repeated half of the LM13700 is shown below.

Diodes Q11, Q12 match Q1, Q2 and form a translinear gain cell . (BJTs are used as diodes for better junction matching.) It has the property that the ratios of currents in the diodes equal the ratio of BJT currents. This is evident when KVL is applied to the diode loop and the BJT input loop. Let i (Q11) = iD− and i (Q12) = iD+ . Then

Also, for a perfect current mirror, i (Q3) = IY = i (Q1) + i (Q2), for α = 1 (β >> 1). The diff-amp output current is differential and is:

Then with this nomenclature, applying KVL to the diode loop,

For matched BJT b-e junctions, Is values match and cancel. Then

Then equating and solving for the current ratios,

It can be shown algebraically that if

then

Applying this algebraic identity to the above circuit equations,

where iX = iD+ iD- . This can also be expressed as a current-gain transfer function;

The translinear cell is a linear differential-input, differential-output current amplifier. Because the static current ratios, IX and IY set the current gain, by varying either of them, the gain is varied. The diff-amp stage output current, through the unity-current-gain mirrors, is the amplifier output current, and the amplifier gain is given as the diff-amp stage gain above. It is inverting because the diodes are common-anode. (An alternative common-cathode connection, with anodes connected to the diff-amp bases, has positive gain.) The LM13700 can be used as a two-quadrant multiplier or VGA.The input circuit is shown below.

This amplifier inputs a unipolar IY and a unipolar (positive) vI . When speed is a consideration, it is best to make vI the gain control and IY (which becomes iY ) the faster waveform. This implementation has a voltage-source input as shown below. When vI = 0 V, then the two sides of the circuit are symmetrical and iD- = iD+ = IX /2.

Let iX be the differential current,

Translinear circuits are easier to analyze using the variable, x , to represent the fraction of current that is conducted by one side. Here let

By KCL,

and thus

The range of x is +/-1. However, to switch all the current from one diode to the other, an infinite differential voltage is required. Because x is a hyperbolic tangent function of vX , the current only asymptotically approaches a complete switchover. Huge voltages are theoretically required to switch decades of currents at near-infinitesimal values. In practice, only about +/-150 mV will switch a differential BJT or diode pair.

Translinear circuit design requires that a design decision be made about the full-scale value of x . The zero-scale value is x = 0.5, where iD+ = iD- . For a choice of x (fs) = 0.75, then the ratio of diode currents is

and ln(3) ≈ 1.009 ≈ 1. The output fraction, iO /IY at full-scale is also 0.5, and the full-scale multiplier (or VGA) gain is 0.5. Therefore, IY must be twice as large as the desired iO .

Substituting into the previously derived equation for vI and applying a KVL equation involving the resistors,

Applying the transfer function, the fractional output current becomes

This equation can be expressed in vI as

To determine the required range for +/-vI , at full-scale let x = 0.75, IX = 100 μA, and R ||RI = 49.9 k Ω Then

The second term in the above equation accounts for the nonlinearity of the diodes in series with resistors. If R ||RI is made relatively large, the first term dominates and the output-current fraction becomes approximately a linear function of the input voltage. If x is restrained to be only slightly larger than 0.5, the currents do not deviate much from being balanced and linearity is maintained.

RI can be chosen for a given vI (fs) and R found from the parallel combination. For vI (fs) = 4 V, then

and

For the output multiplier (U1B) the full-scale gain from the full-scale Y input of IY = 100 μA to the output is IY /2 = 50 μA because (2 x x − 1) at the full-scale x of x(fs) = 0.75 is 0.5. The same full-scale x is used for the multiplier as for the V/I converter (U1A). The vXB inputs are at about

The multiplier Y input is from the Howland current source. Its output current is sourced into the IY (pin 16) input of LM13700 U1B and is

For a potentiometer VP = 10 V, then IYB = 100 μA. The fs gain of the multiplier (with x (fs) = 0.75) is 0.5 and the fs output current is thus 100 μA.

The multiplier X input has a current-source drive instead of a vI , RI drive. However, its corresponding equation is similar:

IXB = 200 μA, twice that of IXA = 100 μA. With a current gain of 0.5, iOA(fs) = iIB (fs) ≈ 50 μA out of the XIN+ node of U1B. With an even 100 μA split between the X -input diodes, an offset of 50 μA makes the X current ratio 150 μA/50 μA = 3 = x /(1 − x), corresponding to x a full-scale x = 0.75.

Output Interface

The IYB = 100 μA is multiplied at fs by −0.5, resulting in an output current of −50 μA (negative current into the IO pin). This current flows through Q5, which has its base at somewhat over the minimum 1.75 V needed for the U1 output to function linearly. Q5 is needed for voltage range extension on the high side, for VP+ ≤ 50 V. The Q5 common-base stage drives a PNP current mirror with a current gain of about one. The output current is at a voltage about a junction drop down from VP+ . The pot emulation falls short of the full range by this drop. This current then develops a voltage across RO = R8 in the isopot circuit diagram. With 0 V of control voltage in, U1A output current is zero as is U1B. i (Q3) = 0 A, R8 has no voltage drop, and VPW = VP- .

At vI = 4 V full-scale, U1A output current is 0.5 x IY = 50 μA. U1B has the same full-scale x = 0.75, and its output current is 0.5 x (VP /R6) = 50 μA. Then this current drops a voltage across R8 of (50 μA)∙(200 kΩ) = 10 V = VP .

Careful examination of the LM13700 specifications indicates from a graph labeled “Voltage vs Amplifier Bias [IY ] Current” that the current gain of the LM13700 amplifiers is significantly less than one in magnitude. After some calculation, the graph indicates that the gain is about −2 to −3 dB below unity gain, or about 20 to 30 % low. This results in the output of the circuit as correspondingly low and can be adjusted either by increasing the bias currents by this fraction (by reducing the value of R2) or by making RO = R8 that much larger.

Prototype Verification

A prototype circuit was constructed as shown below. Test of this circuit is made easier by mounting ICs and BJTs in sockets. Then U1 can be pulled and a 10 kΩ, +/-1 % resistor inserted into pins 6 (ground) and (in order of testing) 16, 15, 1, and 2. The voltage read at pins 16, 1, and 2 should be 1.00 V when VP+ − VP− = 10 V. Adjust VR1 for 2.00 V at pin 15. Replace U1.

Apply a triangle-wave from a function generator to VI (connector pin 3) and ground (pin 4) and adjust for waveform extrema at 0 V and 4 V. BJT Q5 can be pulled and the 10 kΩ test resistor placed from emitter to collector. Set the scope vertical input to ac coupling and measure about 0.5 V pk-pk at the emitter socket. Replace Q5 and observe control voltage and output voltage. They should appear as shown below, where trace 1 is the output and trace 2 is the input control voltage. The output pk-pk voltage should be 10 V but is about 6 V, a −40 % error caused mainly by the low current gain of the LM3700 amplifiers.

If you are using a variable voltage supply for VP , varying it should vary the output amplitude accordingly. Also, an elevated VP can be input by placing a floating 5 V supply in series with the VP supply. The output triangle-wave extremes should then be at 5 V and about 11 V, or 15 V after gain adjustment is applied to the design.

Closure

The rather high output resistance of this circuit can be reduced through an additional emitter-follower buffer stage. The simplest and least accurate way of doing this is to use one of the unused Darlington common-collector amplifiers in U1. The collectors of the Darlington stage connect to VCC .

The high-side range of VPW can be readily extended with an additional supply that is 1 V to 5 V higher than VP+ . Pot terminal loading is (R6 + R7)||R8 ≈ 100 kΩ. This can be reduced by changing the values of these resistors while observing the emulation constraints. As the voltage span, VP , varies, IYB also varies proportionally, maintaining emulation. At high common-mode voltage (VP+ , VP- >> 0 V), the VPW node floats with it, up to the breakdown voltage of Q5 of about 60 V.

1 comment on “An Isolated Potentiometer: The Analog-Actuated Potentiometer, Part 2

  1. salbayeng
    March 18, 2016

    Hi Dennis,

    This is a good explanation of the OTA, the LM13700 datasheet also has many examples.

    I've never used an ATO  in my 40yrs of electronic design , perhaps I will now! 

    I have used a couple of variants of analog multipliers, and multiplexors, and S/H to achieve designs that might have been easier with the LM13700.

     

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