As the technologies continues to shrink the various layout affects continue to worsen. What once was not such an issue for integrated circuits is now problematic. LDE or Layout Dependent Effects are becoming worse as the technology continues to shrink. I am sure many of you have heard about well proximity affects and shallow trench isolation effects, but as the technology continues to shrink we are seeing more issues from pattern density in metal, poly, active, etc. having effects on final circuits. As a result, it has become necessary to include many parameters just to understand how the final circuit will behave. In addition, even what we are familiar with as strictly digital circuits are now needing to be viewed as analog circuits. This is especially true as we continue to increase the speed of our digital circuits. Furthermore, the increase in effects from what were once considered analog affects are becoming more of a difficulty for digital blocks as well.
Many companies are exploiting these affects to speed up the digital circuits through the use of what is called strain engineering. Because these parameters cause strain in the silicon, companies can exploit this fact to increase the speed of digital circuits in an effort to overcome some of unwanted LDE effects. So what does this mean for designers of analog blocks? This to me says if you are designing high performance analog circuits that are sensitive to these parameters it is prudent to design in some type of calibration to your circuits to overcome these unwanted LDE affects or the circuit’s behavior may not be what you simulate.
With this foray into the topic of calibration, might I suggest that the use of calibration of circuits is becoming commonplace for these newer nm technologies? As I have suggested in prior blogs on the topics of modeling, a designer must realize that the models provided will not encompass a 100% correlation to the silicon because there are just too many parameters in the technology to properly capture all of them. It could become a nightmare for the technology team to properly characterize all the needed parameters over the various sizes used in analog circuits. There is just not enough space on SGPC (silicon process monitors) to capture all of the various sizes used in analog circuit design – another topic for a future blog. So what are designers to do with these nm technologies with such significant LDE affects? Calibration is the answer, but what kind? Well, take advantage of the gate density of the process and use as much digital algorithmic calibration as possible.
Implement loop back tests and ways to calibrate top level blocks. This is the preferred method, but occasionally it may be necessary to calibrate individual blocks. This sounds all good but at what cost? The problem with massive calibration algorithms is that they take time to finish. If this time is taken during startup, then significant overhead is possibly chewed up calibrating blocks on the IC. So, how much do we calibrate? Well, if most of the blocks designed are high performance analog blocks then there may be a need to calibrate most everything, but it must be completed in a smart creative way. This means there are new avenues for creativity and patents for the company that can create efficient calibration algorithms that do not take excessive time to complete. Furthermore, the need to calibrate the various analog blocks must be balanced against the area needed for the calibration digital to implement the algorithms. This issue of calibration cannot be underestimated in time, area, and power. The need is there to create algorithms that are area and power efficient and do not take excessive time to complete.
To solve the calibration dilemma, combinations of foreground and background calibration must be explored and combinations thereof. Will technology tooling get to the point where tooling accuracy overcomes the issue of unwanted affects from layouts? Maybe future analog technologies will rely on replication of the various affects to come up with an average affect to reduce these unwanted LDE’s. Such a technology change may be in the use of FinFETs where the sizes are set and the choice for the analog designer is only in the number of the FinFETs the designer can use in parallel to get larger gm’s?
I guess we will have to wait and see what the future brings but I believe digital calibration algorithms are here to stay.
What have your experiences been with the use of digital calibration? Do they work as planned? Or are you limited by unforeseen analog affects such as glitch energy?