Cadence Design Systems has optimized its analog and mixed-signal IC design flow for UMC’s 22ULP/ULL process technologies targeted at 5G, Internet of Things (IoT), and display applications. The UMC-certified design flow from Cadence provides a Unified Reliability Interface (URI), allowing IC developers to monitor the circuit’s reliability and service life when designing chips on UMC’s 22ULP/ULL processes.
The analog and mixed-signal design flow includes an actual demonstration circuit that engineers can apply during IC design to enhance efficiency and precision.
The EDA toolmaker’s design flow—comprising Virtuoso platform for layout, schematic editing, and analog design environment (ADE); Spectre X Simulator and Xcelium Logic Simulation engine; and Voltus-Fi Custom Power Integrity Solution—will be integrated into the process design kit (PDK) for UMC’s 22-nm node.
UMC claims that its 22ULP/ULL process technologies, compared to 28-nm process geometry, can reduce chip die area by 10% while enhancing power efficiency and RF performance. According to Ashutosh Mauskar, VP of product management at Cadence’s Custom IC & PCB Group, that’s crucial in IC designs serving 5G, IoT, and smart wearables.
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