Last time we looked at using ADISimADC in the form of a web-based evaluation tool. As I noted previously, this tool does not require downloaded software to run as it is purely ran from the web. As a reminder, the web-based ADISimADC tool can be accessed online here. Navigating to this web page will bring the user to the page that appears below in Figure 1. The simulator defaults to the first ADC on the list in the drop down box which is the AD9467-250. I received a very good reader question from my last blog post regarding the various parameters that are reported by the tool. Let’s take a look at an example and explore the parameters that are returned. In this example we will look at the AD9643-250.<.p>
For this example, the sample rate is set to 250 MSPS, the analog input frequency is 185.1 MHz, and the analog input level is set to –1.0 dBFS. There are several key ADC performance metrics that are returned by the simulator. These metrics include SNR, SFDR, SINAD, THD, ENOB, Worst Other, and Noise Floor. Let’s take a quick look at each of these. I’ve taken the most commonly used performance metrics and illustrated them in Figure 2 below. I’ll describe these as well as the other parameters that are given by the simulator, but since these are commonly I would like to specifically point them out graphically. I have also marked the process gain which is described below as well.
SNR (Signal-to-Noise Ratio) – This parameter gives the amount of available range between the RMS (root-mean-square) input signal amplitude and the quantization noise floor of the ADC. The theoretical SNR of an N-bit ADC can be found by the equation: SNR = 6.02N + 1.76 dB. For the case of a 14-bit converter, this value is 86.04 dB. In high speed ADCs, this is typically not achieved due to the non-linearities and noise of the ADC. The simulator reports 69.83 dB for the SNR of the AD9643-250. Converting this to dBFS, the SNR is 70.83 dBFS which is on par with the typical value in the data sheet of 70.6 dBFS.
SFDR (Spurious Free Dynamic Range) – This is simply the amount of available range between the available input signal amplitude and the maximum spurious tone found in the ADC output spectrum. This spur can be either a harmonic or some other spurious tone.
SINAD (Signal-to-Noise-and-Distortion ratio) – This is the ratio of the RMS input signal amplitude to the mean value of the RSS (root-sum-square) of all other spectral components including harmonics and spurious tones in the output spectrum excluding any signal content at DC. Generally, the first few harmonics (up to the 5th ) dominate such that higher order harmonics can be ignored. For an ADC with low noise, low harmonics, and low spurious content, the SINAD will be close to the SNR.
THD (Total Harmonic Distortion) – This is the ratio of the RMS value of the input fundamental tone to the mean value of the RSS of all the harmonics. As with SINAD, the first five harmonics typically dominate and are the most significant.
ENOB (Effective Number of Bits) – The ENOB of an ADC is typically found by converting the SINAD using the relationship for the theoretical SNR of the ADC. This parameter gives an idea of how many ‘real’ bits are available from the converter. For a 14-bit converter, the theoretical SNR would be 86.04 dB, but as we can see from the AD9643 example the SNR is really 69.83 dB. To approximate the ENOB we use SINAD in the following equation: ENOB = (SINAD – 1.76)/6.02. For the AD9643 in this example, ENOB = (69.63 – 1.76)/6.02 = 11.4 bits (which is slightly higher than the simulator returns since the simulator takes more factors into account which is beyond the scope of this blog).
Worst Other – This is simply the worst spurious tone in the ADC’s output spectrum outside of the reported harmonics. In this example, this could be the 6th or higher harmonic or some other spurious tone that is not harmonically related to the input fundamental tone (in the simulation shown above the worst other is sufficiently low that it is not reported).
Process Gain – This is defined by the depth of the FFT. For an FFT of depth M, the process gain is given by the equation: Process Gain = 10×log(M/2). For a 32k FFT, the process gain is 10×log(32768/2) = 42.14 dB.
Noise Floor – The noise floor of the ADC is found by summing the SNR and the process gain. In this example, the SNR of the AD9643 is 70.83 dBFS and the process gain is 42.14 (the simulator generates a 32k FFT). This yields a noise floor of 112.97 dB.
For a more in depth review of the typical performance metrics of a high speed ADC, please refer to a few excellent application notes written by Walt Kester – MT-001 and MT-003. In addition, there is some great information available in the application note AN-835 High Speed ADC Testing. These provide some additional details that are beyond the scope of what can reasonably be covered in the short space available for this blog post. I’d encourage the reader to take some time to look through these documents to gain a more in depth understanding of the performance metrics that are used to specify a high speed ADC. Thanks for the great questions, please keep them coming and stay tuned as we continue to look at design tools available from Analog Devices.