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Analog experts eye Moore’s Law

SAN DIEGO ” A panel of analog and process experts looked at the challenges posed by Moore's Law and concluded that something's got to give.

Charlie Sodini of Massachusetts Institute of Technology opened the Design Automation Conference panel here by sketching a grim picture. Arguing for separate and unequal treatment, Sodini said “Integration isn't always the answer. We can't keep using silicon as a packaging technology.”

Sodini added that lower supply voltages mandated by fine process geometries put pressure on signal-to-noise ratios. Circuit designers responded by increasing the power of circuits, thus undoing the advantages of scaling. In addition, he said, engineering of the gate dielectric materials is creating more trap sites, driving up both 1/f and white noise.

Moreover, he said, leakage was limiting resolution, especially that of discrete-time circuits, which are based on the assumption that it is possible to store charge efficiently. “Running the circuit faster helps, but again that drives up power,” he said. “We are watching 20 years of charge-storage circuit design technology leak away.”

IBM's Tony Bonaccio didn't dispute the problems. In “designing chips for mass storage and then selling maybe 30 million of one part, we have to face the fact that in the market, integration always wins,” Bonaccio said. “But we can't keep up with Moore's Law by scaling ” our designs don't scale. We have to keep up by innovation.”

Bonaccio said that means aggressively moving functions from analog to digital. “That's what we will have to do in the future,” Bonaccio concluded. “Minimize the number of analog components, and use the relatively free digital stuff to fix it up ” autocalibration, analog built-in self test.”

Ernesto Perea of ST Microelectronics research laboratories, said he is pessimistic about the future, adding that the passive components that set the minimum size of an analog block do not scale. Hence integrated analog necessarily becomes more expensive as geometries decline. “In the long run, it becomes impossible,” Perea said.

Bob Pitts, Texas Instruments' 90-nm platform manager, joined Bonaccio in the positive camp. “At TI, analog and RF circuits are shrinking in area right along with digital,” Pitts said. “That isn't scaling. It's architectural innovation, done from the system level down.”

Pitts described partitioning decisions by system designers, novel circuits and process adders by the foundry engineers working together to reach objectives like so-called single-chip cellphones. He said TI's architectural arsenal has been expanded to work around them.

TI'has shifted to controlling and calibrating analog circuits with a dedicated ARM processor, he said. The approach was recently upgraded to a proprietary 64-bit RISC core that actively adjusts the linearity of RF circuits. TI has also developed on-chip, low-drop-out (LDO) regulators for precision voltage supply, and is moving to an LDO-per-block architecture for critical RF and mixed-signal functions.

On the process side, Pitts said many devices required by analog designers could be made with no additional masks. “Virtually free is a necessity at our volumes,” he said.

Added Stanford University professor Theresa Meng: “We are using logic circuits to calibrate and correct analog circuits. But with digital circuitry being so much smaller and using one twentieth the power, tomorrow we will be asking ourselves just how many analog transistors we need to keep at all.”

“We have to challenge traditional design,” Meng added. “We can do self-calibrating circuits that continuously correct distortion. This takes new topologies and new digital algorithms for statistical signal processing. But it is the future of analog.”

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