Analog Integration on 65 nm – Online Chat Reminder

We are having an online chat on August 22. The title is Analog Integration on 65 nm: How Low Can We Go? This discussion is based on a recent blog by Steve Taranovich, Does Analog Integration Really Need to Go Beyond 0.18μm?.

With smaller sizes come lower breakdown voltages. For the digital circuitry on a chip, the lower breakdown voltage doesn't pose much of a problem, except possible noise infringement on digital low/high thresholds. But for analog circuitry, lower breakdown voltages can be trouble — the voltage span available for analog signals is reduced. With that comes degraded signal-to-noise ratio.

However, smaller size and lower voltage span helps in circuits that are intended for high-speed applications — the ultra-high-speed ADCs and RF functions.

Join us next week to discuss these and other pros and cons regarding the smaller and smaller geometries being used. The chat (similar to using an instant messaging system, but in this case browser based) will start at 11:00 a.m. EDT on Thursday, August 22. We will have Eric Naviasky, a fellow from Cadence on hand to help with our discussion.

All you have to do is to click here at the appropriate time to join the discussion. Note: If you aren’t already registered on Planet Analog, register in advance to speed things up. Registration just takes a few minutes. We look forward to seeing you next Thursday. Bring your questions and comments.

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2 comments on “Analog Integration on 65 nm – Online Chat Reminder

  1. samicksha
    August 22, 2013

    Although Global Time Gap, dosent make me much comfortable to join the chat but i will try to there in chat room, sounds really interesting to hear about breakdown voltages and a degraded signal-to-noise ratio.

  2. Brad_Albing
    August 22, 2013

    Uh-oh – sorry you missed the chat. Next time I'll post the time in GMT/UTC to avoid confusion.

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