Analog Integration on 65 nm – Online Chat

We are having an online chat on August 22. The topic is Analog Integration on 65 nm: How Low Can We Go? This discussion is based on a recent blog by Steve Taranovich, Does Analog Integration Really Need to Go Beyond 0.18μm?

With smaller sizes come lower breakdown voltages. For the digital circuitry on a chip, the lower breakdown voltage doesn't pose much of a problem except possible noise infringement on digital low/high thresholds. But for analog circuitry, lower breakdown voltages can be trouble — the voltage span available for analog signals is reduced. With that comes a degraded signal-to-noise ratio.

However, smaller size and lower voltage span helps in circuits that are intended for high-speed applications — the ultra-high speed ADCs and RF functions.

Join us next week to discuss these and other pros and cons regarding the smaller and smaller geometries being used. The chat will start at 11:00 a.m. EDT on Thursday, August 22. (It's similar to using an instant messaging system but in this case browser based.) We plan on having a few industry experts on hand to help with our discussion.

All you have to do is to click here at the appropriate time to join the discussion. Note: If you aren’t already registered on Planet Analog, register in advance to speed things up. Registration only takes a few minutes. We look forward to seeing you next Thursday. Bring your questions and comments.

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4 comments on “Analog Integration on 65 nm – Online Chat

  1. goafrit2
    August 18, 2013

    When you move below the 100nm CMOS domain, the whole static power and interconnect issues begin to manifest at a deeper level. We will surely learn more in this chat.

  2. Brad_Albing
    August 18, 2013

    @goafrit2 – Yes – this should be a good chat regarding learning about smaller and smaller geometry layout processes and the consequencies of same.

  3. Netcrawl
    August 19, 2013

    Pretty exciting, I can't wait to have this chat. I think I need to set my “analog clock” for chat time. @goafrit2 I think we will learn more on that in the chat. 

  4. SunitaT
    August 20, 2013

    With the lesser geometry, the supply voltage had to be reduced to prevent voltage interruption. Unfortunately, this led to a bigger gate-switching delay in digital circuitry and lower dynamic range in analog circuits. Process designers dropped FET gate threshold voltage to recompensate for the switching delay problem. In the analog empire, scaling did not bring much area reduction. Though, it did yield higher-speed transistors, which led to silicon implementation of RF circuitry and high-speed analog blocks such as ADCs and DACs.

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