Analog IP reuse, one of the biggest challenges facing system-on-chip (SoC) designs, is getting some help from successful migrations to smaller process nodes. Thalia Design Automation, for instance, has announced the completion of its analog IP portfolio’s migration to the 22-nm process node.
The Cambridge, UK-based company claims to have migrated analog IPs via its automated AMALIA IP reuse platform. Thalia is targeting its 22-nm analog IP reuse applications mainly at audio and power management analog IPs.
Why does analog IP reuse engagement to a new process node matter? For a start, smaller process nodes like 22 nm promise significantly lower leakage. Next, the compliance to new technology or process node can reduce the number of iterations required to reuse an IP in a new node.
Figure 1 Analog IP reuse solutions demand a major overhaul in analog and mixed-signal design flow methodology. Source: Thalia Design Automation
An analog IP block becomes unusable when it fails to meet the requirements in the target technology. That’s why analog IP reuse is a tough nut to crack. Not surprisingly, therefore, a lot of effort involved in migrating an IP from one process node to another is associated with qualifying the IP in the target technology.
Sowmyan Rajagopalan, CTO of Thalia, says that analog design doesn’t have to be black art with the availability of advanced design automation tools that dramatically streamline analog design flow and create an analog IP reuse methodology. “That leads to a fundamental shift in the way analog IP is created and delivered.”
Fabrication technology nodes have been a key barrier for analog IPs as the decision to move IPs from one process node to another requires a structured methodology. The solution, according to Rajagopalan, lies in a combination of automation tools and advanced methodologies.
Figure 2 Advanced methodologies allow analog IP to migrate from one process node to another in less time. Source: Thalia Design Automation
Earlier, in September 2020, Thalia announced an upgrade to its AMALIA IP reuse platform to cut the cost of qualifying IP in a target technology. Technology Analyzer identifies the root cause of discrepancies between base and target technologies rapidly and accurately. “That’s how it enables designers to see where the process technologies are similar and where they differ the most,” Rajagopalan added.
The fact that analog and mixed-signal IP blocks can be reused across multiple chips on multiple technology nodes is a welcome relief for SoC designers seeking to establish a more structured methodology. It’s imperative in their bid to bypass the need for highly skilled and scarce engineering resources and avoid relatively long design cycles and often multiple design iterations to get to a production product.
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