The Mobile Industry Processor Interface Alliance (MIPI) is becoming more prevalent in the mobile device product industry. Mobile devices now commonly have dual display and/or dual camera architectures, particularly in the mid and higher functionality end products. The MIPI standard was originally defined as a point-to-point architecture, and consequently first generation processors, sensor modules and displays had a single MIPI port.
This article describes how, with the use of analog switches, the legacy processors can easily interface with dual cameras or dual displays without impacting the current system architecture and can, in actuality, enhance system performance by isolating the transmission line effects of the second camera (or display) loading the MIPI bus. In addition, the use of analog switches, due to their bidirectional capability, can also be used to multiplex co-processors to a single camera or display without impacting the performance.
As the new concept phones move to three displays, even the newer processors with 2x MIPI ports will benefit from an analog switch multiplexer device. Therefore, understanding the use of analog switches and their merits will enable the retrofit or upgraded feature set mobile devices to be designed with legacy or next generation processors.
The mobile-device trend spurring the problem
Before delving into the details of switch applications, we will briefly summarize some of the trends in mobile devices that may facilitate the use of analog switches.
Consumers want access to information as quickly and efficiently as possible – whether it’s the status of their cell phone battery; the weather; the time; stock quotes; e-mail; or text messages – and they prefer not to have to open the flip or slider of their phone to get to this information. A smaller display (AMOLED or E-ink perhaps) can provide that option when not actively using the main touch screen display, which is often reserved for browsing, video conferencing, music and application controls. An analog switch can support such multiplexing.
For dual-camera applications, as a consumer we want to capture those spontaneous moments and put them on “film” (or video), and we may have a high-resolution 12 megapixel (MP) camera and a 5 MP camera available in our phone. For social networking, you might want a videoconference capability (webcam) utilizing 3G technology as a part of the feature set in your future phone. An analog switch can support a more robust electrical interface between the dual cameras, by multiplexing and isolating the camera-data paths.
So how does the analog switch fit into the MIPI architecture? The analog switch can be viewed as either (a) a media channel as part of the Transmission Line Interconnect Structure (TLIS) or (b) part of the MIPITransmitter (Figure 1 ). In reality, they are one and the same, but from the perspective of characterizing the analog switch for Interoperability, it is better to consider the switch as part of the TLIS so that its S-parameter characteristics can be accurately determined. If considering it to be part of the transmitter, then the Interoperability D-PHY Transmitter Conformance test suite would be run.
Figure 1: The analog switch as part of a MIPI system
(Click on image to enlarge)
System designers are often wary of inserting an analog switch in point-to-point bus architectures for fear that the insertion loss introduced may cause a system or interoperability failure. This hesitation has been greatly reduced in recent years by the tremendous utilization of analog switches in the USB environment when multiplexing USB, UART or audio data onto the USB connector. The same migration and confidence can be instilled in MIPI architectures.
It is true that the RC characteristics of the analog switch need to be considered, but a more important factor is to have good PCB design to minimize discontinuities and match impedances. Additional factors to good signal integrity using the analog switch include the processor characteristics (particularly IOH /IOL ), flex cable and connector design, additional filter/ESD devices, terminations and bus load.
Figure 2 shows a traditional, legacy “shared” parallel-bus architecture for a dual camera (high and low resolution) and its incident wave response. There are discontinuities in the waveform as the signal travels between the processor and camera modules. Any discontinuities in the rising or falling edges will result in failing the MIPI specifications for interoperability.
Figure 2: Dual-camera architecture with shared bus
(Click on image to enlarge)
The dual camera environment of Figure 2 can be easily validated by driving 2 MIPI Receiver Termination Boards (RTB) that are both powered and terminated. The reflections will result in degradation in the edge rate as the system moves from Low Power (LP) to HS traffic mode. This degradation also occurs for the amplitude and edge of the differential signals when in HS traffic mode, which then results in a closing of the eye. If one of the RTBs is turned off or un-terminated, the degradation also gets worse, further closing the eye.
(Part 2 will look at the various solutions and their key attributes, as well as the PCB layout.)
[Note : MIPI word marks and logos are trademarks owned by Mobile Industry Processor Interface (MIPI) Alliance, Inc. and any use of such marks by Fairchild Semiconductor Corp. is under license. The MIPI Alliance is an industry initiative established to define and promote open standards for hardware and software interfaces in mobile terminals. Other trademarks and trade names are those of their respective owners.]
About the authors
Tony Cheng Han Lee is an applications engineer for the Mobile Solution Signal Path Analog Switch Group at Fairchild Semiconductor Corp. Tony graduated from the University of California, Riverside, with a Bachelor of Science degree in Electrical Engineering.
Graham Connolly is a principal applications, modeling, and product-definition engineer at Fairchild Semiconductor Corp. Graham originally joined Fairchild as a design engineer in 1984 and has worked in bipolar, ECL and CMOS technologies before moving into the realm of product definition. Recently his focus became MHL and MIPI, after supporting USB for many years. Prior to joining Fairchild Semiconductor, Graham was employed at GEC Hirst Research Centre, Wembley UK, working on image processing chips using CMOS SOS technologies. Graham has an Msc (Hons) in Micro Electronic Systems Design from Brunel University, Uxbridge, UK.