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Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)

(Part 1 looked at the nature of the problem, as well as the requirements of D-PHY MIPI® dual camera/dual display applications, click here to read it.)


What is the solution?

The solution is to add an analog switch.

When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good “eye” performance by minimizing reflections and edge rate degradation. Initially, the extra CON /COFF of the switch may be viewed as a detriment to the system performance, but in reality, removing the discontinuity reflections outweighs the extra capacitance and series resistance incurred by inserting the analog switch.

The MIPIspecifications use a 0.3 UI (unit interval) for the criteria of Interoperability, so the faster you want to run your system, the more critical the switch CON /COFF characteristicsbecomes, since that is the parameter that will impact the edge rate and, therefore, the 0.3 UI criteria.

Even if the 0.3 UI is not met, it does not mean that the insertion of the switch will result in system failure or not passing Interoperability. The switch RON impacts the voltage drop between transmitter and receiver, so receiver (Rx) Sensitivity thresholds need to be met when inserting the analog switch.

Typically, this is of less concern due to the low current driven through the switch and is usually 10mV or less of a voltage drop (< 5% of voltage swing).Figure 3 . Waveform 1 highlights the potential effects of too fast of an edge rate (<150psec); waveform 2 is the optimum, where the edge rate is < 0.3 UI; and waveform 3 shows the effects of too high a capacitance that can result in an edge rate outside of the MIPI specification.


Figure 3: Incident-wave characteristics for inserting an analog switch
relative to MIPI eye

(Click on image to enlarge)

It should be noted, however, that even though the waveform 3 edge rate may not meet the recommended numeric value for MIPI Inter-operability with the D-PHY specification, the system can still fully function and meet the “eye” diagram. This is where prototyping in the actual phone PCB design is the final interoperability “compliance” test. Oftentimes, the environment has a greater impact; therefore, good PCB design (via, connectors and correct differential impedance), choice, and placement of devices are paramount.

So how do I convert the legacy parallel bus architecture of OR’ing the camera modules (Figure 2) into a more robust system with dual cameras (or LCD)? The first option is to insert a camera isolation switch such as the Fairchild FSA1211.

Figure 4 describes the incident-wave response for SPST analog-switch (FSA1211) parallel architecture in a dual-camera application, which results in improving the system performance by reducing the reflections through the isolation of the stubs and discontinuities. In this example, the low-resolution camera and its capacitance are being isolated when the high-speed, high-resolution camera is transmitting.


Figure 4: Dual-camera application with SPST isolation switch
(Click on image to enlarge)

When the low-resolution camera is enabled via the SPST switches, the high-resolution camera stubs have less of an impact due to the processing speed of the low-resolution module. As can be seen from the oscilloscope trace, the waveform discontinuities and ringing have been almost removed when transmitting to the high-resolution camera.

With the advent of the MIPI D-PHY, a serial interface is now used to replace the parallel bus but the same concept of using analog switches for isolation in a dual camera/display application applies.

A further, more optimal, improvement that ensures complete isolation between serial architecture camera modules ( Figure 5 ) is to use SPDT analog switches (such as FSA642). This is particularly recommended for dual high-resolution camera applications. Whichever path of the analog switch is enabled is determined by the camera module/processor software stack, which then uses a GPIO (general-purpose input/output) pin to toggle the multiplexer.


Figure 5: Dual-camera application with SPDT multiplexing switch
(Click on image to enlarge)

This analog switch is also specifically configured to multiplex a single MIPI port processor Clock and 2-Data Lane architecture to dual cameras or LCDs. For example, as the consumer opens the flip or slider, the small external AMOLED display turns off and the main display is turned on to display the application icons. Being bidirectional in nature, it can also be used to multiplex a single camera or display to dual processors.

With the isolation of the non-transmitting camera path, there will be no degradation on the rising and falling edges due to reflections, when transitioning between LP and HS traffic mode, and the eye remains open. This architecture is also applicable to dual-display applications.

Interoperability testing of the analog switches as both a media channel or as part of the D-PHY Tx has proven performance at a minimum of 800 Mbps.

To further improve system performance, it is very important to pay attention to detail with respect to the physical board and layout to minimize the impact on signal integrity.

PCB Design and Layout

In addition to the typical considerations of PCB trace-matching –such as minimizing stubs, maintaining differential impedance of 100 ? ± 20%, minimizing vias and avoiding 90º trace routing–there are other recommendations that are a function of the PCB material and the number of signal layers.  

Some key recommendations include:

  • Route primary differential signals first, and on an adjacent signal layer to the GND plane, with lengths matching to within approximately 1.0 – 1.5mm;
  • Maintain differential signal trace lengths to be less than 75mm (25mm preferred);
  • Avoid common-mode chokes on differential signal lines unless essential for EMI;
  • Utilize micro-strip and strip line guidelines, such as isolating differential serial lines with adjacent grounds; and if a signal must cross the high speed differential signals, then ensure it is done in a perpendicular manner

The MIPI analog switches discussed in this article, with rise/fall times of 150-450ps for HS traffic, should be placed as close as possible to the MIPI controller or driver output. The VCC decoupling (0.1 μF and/or 1 μF) should also be placed as close to the switch pin as possible.

To conclude , system engineers should not be fearful that analog switches inserted between the D-PHY transmitter and receiver will result in problems. On the contrary, analog switches optimized for MIPI D-PHY system environments, in concert with good SI techniques and board design, enable designers and product manufacturers to take advantage of rapid feature expansion through multiplexing relevant data sources.

With a correct understanding of the characteristics of optimized analog switches, and the importance of each in a MIPI environment means that very robust designs can be created. The high performance MIPI switches discussed in this article offer a portfolio of products (such as FSA642) that are matched well to MIPI D-PHY signal paths in the ultra-portable and consumer products, while maintaining signal integrity and optimizing key consumer specifications.

For more information about Fairchild Analog switches for camera and MIPI applications, visit www.fairchildsemi.com/cameraswitch.

[Note : MIPI word marks and logos are trademarks owned by Mobile Industry Processor Interface (MIPI) Alliance, Inc. and any use of such marks by Fairchild Semiconductor Corp. is under license. The MIPI Alliance is an industry initiative established to define and promote open standards for hardware and software interfaces in mobile terminals. Other trademarks and trade names are those of their respective owners.]


About the authors

Tony Cheng Han Lee is an applications engineer for the Mobile Solution Signal Path Analog Switch Group at Fairchild Semiconductor Corp. Tony graduated from the University of California, Riverside, with a Bachelor of Science degree in Electrical Engineering.

Graham Connolly is a principal applications, modeling, and product-definition engineer at Fairchild Semiconductor Corp. Graham originally joined Fairchild as a design engineer in 1984 and has worked in bipolar, ECL and CMOS technologies before moving into the realm of product definition. Recently his focus became MHL and MIPI, after supporting USB for many years. Prior to joining Fairchild Semiconductor, Graham was employed at GEC Hirst Research Centre, Wembley UK, working on image processing chips using CMOS SOS technologies. Graham has an Msc (Hons) in Micro Electronic Systems Design from Brunel University, Uxbridge, UK.

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