Analog Synthesis: Ready for Prime Time?

Being able to automatically synthesize analog circuits from a
set of specifications has long been the dream of many analog
designers. Recent announcements from some analog EDA companies are
bringing this dream closer to reality.

Analog vs. Digital Synthesis
One of the milestones in digital-chip EDA tools was Synopsys' commercialization of logic synthesis in
the mid-1980s. Logic synthesis allowed digital designers to
automatically generate a gate-level representation of a circuit,
according to a set of timing constraints, from a register-transfer
level (RTL) description. This architectural-to-structural
conversion results in a huge improvement in design productivity,
allowing a designer to shift much of their chip's design effort
from the gate level to RTL.

A corresponding operation for analog design, analog synthesis,
is a much more difficult operation. While digital synthesis
operates under timing, power, and some signal-integrity
constraints, analog synthesis has a much larger design space in
which to operate. Along with the constraints faced by digital
designers, analog designers have to deal with constraints such as
jitter, voltage offset, slew rate, output impedance, noise
restrictions, and several others. This makes the “tuning” of
synthesized analog circuits, involving tasks as transistor sizing,
component value optimization, and bias setting, a much more complex
problem than that of choosing logic functions from a digital-cell
library for a synthesized digital circuit.

The need for analog synthesis is particularly important for
mixed-signal system-on-a-chip (SoC) designs that comprise digital
and analog circuitry. Whereas the digital blocks of an SoC are
generally designed “top-down”, concentrating on RTL and above, the
analog blocks are usually done “bottom-up”, by hand, at the
transistor level, dependent on the expertise of the analog
designer. Complicating the design process is the lack of
pre-designed analog-function blocks, or analog silicon-IP (SIP),
compared to digital SIP. Hence the analog-design piece of a
mixed-signal chip consumes an inordinate percentage of the chip's
total design time. However, help is on the way in the form of new
software tools for analog synthesis and the generation of analog

New Analog-Synthesis Developments
Analog Design Automation (ADA) has two offerings
in its new Genius product line. The new products are Creative
Genius, which creates entire databases of optimized
analog/mixed-signal SIP, and IP Explorer Genius, a tool for
analyzing and selecting the SIP. For Creative Genius input, a
designer inputs the following:

  • Transistor-level netlist —Obtained from a schematic
    developed with EDA tools such as those provided by Cadence or Mentor
  • Testbenches —Sets of stimuli and expected responses
    for the circuit
  • Design objectives (specifications) —Parameters such
    as output impedance, slew rate, circuit area, and power
  • Process and external variations —Temperature, drive
    load, voltage, process variations, and others
  • Design variables —Includes transistor sizes and
    resistance and capacitance values.

From this information, the tool simultaneously looks at all the
design specifications and creates all the sized-circuit solutions
that meet the designer's specifications, including corner

Once Creative Genius has created a spectrum of viable circuit
optimizations, IP Explorer Genius evaluates the created circuits
using an N-dimensional color graph that displays all the results (N
is the number of design objectives). The designer than evaluates
the tradeoffs between the different circuits with respect to the
total design-objective space and selects the desired circuit. IP
Explorer Genius takes this circuit, inserts component values
(including transistor sizes) into the netlist, and back-annotates
the circuit's schematic—the circuit is now ready for layout.
Figure 1 shows how the Genius tools fit into an analog
design flow using Mentor Graphics and/or Cadence analog-design
tools. ADA recently announced that they have integrated their tools
into Mentor's Design Architect-IC/Eldo design flow. In this flow,
you use Design Architect-IC for schematic entry and Eldo for
simulation, allowing the data generated by ADA to be automatically
checked against the Eldo's results.

Figure 1:  ADA Genius integrated into the existing analog/mixed-signal design flow. Creative Genius takes a design netlist and constraints from the user. From these inputs, the tool generates a set of possible circuit options that the user evaluates using IP Explorer Genius.

While ADA has concentrated on the design
front-end—specifications to optimized circuit—Barcelona Design has a couple of new tools that go
from design specs all the way through analog-circuit layout.
Barcelona's answer combines two software products—Prado, a
“one size fits all” synthesis platform and various synthesizable
analog-circuit engines. Each engine represents circuit topology to
achieve a specific functionality along with process-specific models
that Barcelona has developed for accurate and rapid circuit
synthesis (Figure 2 ).

Figure 2:  Barcelona's Prado synthesis platform works with synthesizable
analog-synthesis engines, each engine representing circuit topology for a specific functionality along with process-specific models. Prado generates behavioral models of an optimized circuit with, optionally, a placed-and-routed design.

Prado synthesizes the optimized circuit in two ways, with and
without generation of a placed-and-routed physical design. The
engine does no simulation of the circuit it synthesizes, Barcelona
stating that the circuit is “correct by construction”. In addition,
there are two flavors to Prado's output—”exploratory” (let's
see if I like this one) and “finished” (this one is definitely the
one I want to use). Exploratory instances comprise behavioral
models and datasheets and are at no cost to the designer. A
finished instance comprises a netlist, place-and-routed GDS-II
file, and pin information—this instance incurs a per-use

Prado can accommodate multiple solving engines for its synthesis
and, according to Barcelona, is super fast—the engine can
solve millions of equations and constraints in just a few hours. A
fully placed-and-routed design of a complex analog block takes just
minutes. One drawback for the engineer who likes detailed design
checking: Prado does not create a Spice model of the optimized
circuit. If you want to simulate the design, you need third-party
tools to extract a model from the physical database.

Each circuit engine, based on a single topology and single
silicon process, requires a separate license. The only engine
available at this time is the Miro Class clocking engine, designed
for TSMC's 0.18µm CMOS process. Miro comprises clock generation and
clock synchronization functions and topology, and supports PLL
designs up to 2 GHz with jitter as low as 5ps and power dissipation
under 5mW.

Genius vs. Prado/Miro
ADA's Genius products, along with Barcelona with Prado and Miro,
are important steps on the path towards the “perfect”
analog-synthesis engine. Both companies' tools can synthesize
optimized parameter values to meet a set of design constraints.
ADA's Creative genius needs, as one of its inputs, a user-defined
netlist that defines a circuit topology. The tool then adjusts
component values to define a set of circuits to meet the user's
constraint set. Miro inherently defines the topology of a class of
analog circuits (clocking engines)—this topology then
undergoes optimization, again to meet a set of design
specifications. Neither tool actually synthesizes “from scratch”
topology, just optimized component values (although Miro does vary
some topology details, dependent on design specifications).

Prado can produce a layout of the optimized circuit. ADA does
not have a physical-design tool, requiring the user to use a
third-party analog-layout tool for physical implementation.

Genius appears to be more flexible than Prado/Miro. Genius
accepts user-defined topologies—the tool's success depends on
the designer's expertise. The value of the Genius tools is that
they can create a large number of circuits, with a common topology
but different component values, in a relatively short time, thus
allowing the designer to pick the optimized circuit, with its
inherent tradeoffs, that best meets a set of design objectives.

Prado depends on the availability of Barcelona circuit engines
and hence the design expertise of Barcelona's own developers. At
this time, there is only one engine available—Miro—for
clocking circuits. Barcelona promises additional engines for data
conversion (ADCs and DACs), op amps, bandgap references, and RF
components, but has not disclosed a schedule for availability of
these engines.

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