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Applying Duty-Cycle Control to Save Power

Shutting down inactive circuitry can save substantial power; however, this kind of power management assumes there is an actively managing “brain” (typically a microcontroller) that knows when to turn things on and off. In extremely low-power systems running at sub-microamp levels, it may be desirable to let the microcontroller remain in a deep sleep mode and, instead, let a simple, ultra-low-power clock wake circuitry at periodic intervals.

While many microcontrollers have such timers, a simple analog clock built from an extremely low power comparator can run at lower power, removing the need for powering up from the interrupt timer and in some cases eliminating the need for a microcontroller altogether. As well, the analog clock may operate from low voltages — as low as 1V from a single cell — and provide a periodic boosted voltage without need for a separate regulator.

The circuits shown here are based on a simple relaxation oscillator utilizing a very low power comparator. Running at around 500 nanoamps, the oscillator is configured as a very low duty cycle clock, used to duty-cycle power to circuitry in small bursts. Periodically the clock goes “high,” circuitry is enabled, and power is delivered; while most of the time the clock stays low, the circuitry is not powered, leaving only the oscillator running as an “always on” duty-cycling clock.

The basic oscillator design is shown in Figure 1.

Figure 1

A very low-power analog comparator (TSM9119) provides a very low-power clock for applying duty-cycling control.

A very low-power analog comparator (TSM9119) provides a very low-power clock
for applying duty-cycling control.

The timing is set up as follows: First, the upper (VUPTHR ) and lower (VLWTHR ) hysteretic trip thresholds are set with R1, R2 and R3:

Then, R4 can be chosen according to the desired off-time:

And R5 is chosen according to the desired on-time:

Note that since VUPTHR and VLWTHR are just a scaling of VBATT , neither TON nor TOFF are dependent on VBATT .

The TSM9119's input bias currents of less than 2nA (across temperature) enable the use of high-value resistors. Use of 10MΩ resistors yielded less than 30mV net offset referred to the comparator inputs. Many off-the-shelf bipolar transistors can be substituted for Q1 and Q2: However, gold-doped discrete transistors (most 2N3904 and 2N3906 transistors are not gold-doped) should be avoided because gold doping increases leakage currents.1

All capacitors should be ceramic for lowest leakage, generally limited by the case resistance. The circuit performs well even at hot temperatures, where leakages typically increase. Using a capacitor with an NP0 (C0G) dielectric improves frequency stability, and further reduces dielectric absorption issues. (Dielectric absorption can cause the capacitor to “remember” its charge when charged and discharged in the circuit; however, this is not meant to be a precision timing circuit, so the use of a C0G should be considered optional.)

Table 1 shows currents measured for the duty-cycling clock shown:

Table 1

What are some uses for this clock? Perhaps most obvious, the oscillator could serve periodically as a clock to wake a microcontroller. While most microcontrollers have built-in interrupt timers, not all have supply currents as low as this. The microcontroller could be set to a deep-sleep mode, woken up by the duty-cycling clock to check periodically system status.

This “duty-cycler” might further enable current savings by periodically powering a simple measurement, the results of which then in turn wake a microcontroller. Thus, the microcontroller only wakes upon a result where it needs to take action — not simply whenever the timer interrupts it.

Figure 2

A nanopower solar detector implementing duty-cycle control to keep power consumption low.

A nanopower solar detector implementing duty-cycle control to keep power consumption low.

Figure 2 shows such a scenario — in this case, a solar monitor checks the availability of sunlight, perhaps for a low power solar-powered system that should not turn until enough light power is available. The duty-cycling clock circuit provides power to the solar detector, comprising U2 and U3 and associated passives, at intervals of about 1 second. In the solar detector, photodiode D1 senses available light, and a TS1001 op amp sinks the resulting photodetected current through its VSS power supply pin, providing a positive polarity signal.

In the op amp loop, the op amp must consume power supply current according to the photodetected current (effectively canceling it); this current can be higher than 30µA. However, since the solar detector does not need to be continuously on, the duty cycling clock circuit reduces this current by the factor of the duty cycle (approximately 500), resulting in a net average current consumption of the detector to less than 100nA. The TSM9117 is a voltage detector IC, where its output goes high when the input rises above 1.25V, indicating enough light is present and interrupting the processor. The desired sensitivity trip threshold voltage can be set by choosing R9.

The “duty-cycler”can be further configured to provide burst power at a boosted output voltage to the load. Here, the idea is to generate short bursts of higher voltage, employing a simple voltage doubling boost capacitor integrated into the clock design. The boost cap provides the higher voltage only for the short duration for which it is actually needed, eliminating the need for a separate boost converter and its associated overhead quiescent currents and delays (in fact some converters' shutdown current exceeds the currents used by this duty-cycling clock).

Figure 3

One technique to boost voltage using duty-cycle control.

One technique to boost voltage using duty-cycle control.

Figure 3 shows the previous idea in a real-world example. Here, the circuit periodically transmits an identifying code, utilizing a 433MHz SAW resonator transmitter. The duty-cycling clock provides the timing for the bursts by enabling a logic pattern generator (could be a fed-back, shift-register-based code generator) to feed the transmitter with an OOK (on-off keyed) signal for transmission. As a bonus, the clock provides the transmitter with approximately doubled voltage (3.3V) during the clock's “on time,” enabling the SAW resonator to transmit at a reasonable transmit power level.

Footnote:
1. Troubleshooting Analog Circuits by Bob Pease, page 66.

To Page 2

Capacitor C3 serves as the charge pump's flying capacitor, with the lower side of the capacitor driven by Output A of the flip-flop, which functions as the duty-cycler clock. The capacitor charges through Schottky diode D1 when the Output A is low; the VOUT rises to approximately 2 X VIN (minus the D1 diode drop) when the Output A is high. Q3 clamps the bottom of C3 to VIN when the Output B is high, completing a low impedance, series-connected path of C2 and C3 as the double-stacked supply capacitors to power the output.

The values of C2 and C3 should be chosen to support the load and on-time duration needed for VOUT . C2=C3=100μF was chosen for this design, which provided a minimum of 3V during the “on time”of 500μs for a 25mA load. Q4 provides an optional load cutoff; however, the SAW resonator transmitter does not need to be disconnected in this way since it draws virtually no current when the logic pattern generator provides a “zero”level.

Logic gates U2 and U3 add some timing adjustments to the duty-cycling clock. Output B is not enabled until Output A goes high. Output B falls before Output A, thus ensuring break-before-make timing for Q3. Additionally, this timing ensures that the pattern generator does not start until the SAW resonator transmitter has had some time to settle with its boosted supply voltage, and that it stops transmission before the boosted voltage is removed from the transmitter. “AUP”family logic is used for low supply currents over temperature.

Figure 4

'On-time' waveforms for the circuit in Figure 3.

“On-time” waveforms for the circuit in Figure 3.

The “no load”currents measured in the circuit show almost no overhead increase with the added boost circuitry, and the loaded currents reflect the 3.5mA average load current drawn by the transmitter during the 500μs burst period. See Table 2.

Table 2

At hot temperatures, the circuit's one vulnerability is the parasitic leakage currents of Q3, a BSH205 MOSFET. If this is a concern, the BSH205 may be changed to a PNP transistor at the expense of a slightly reduced boost voltage.

Figure 5

How to apply duty-cycle control to boost power from a single 1V cell.

How to apply duty-cycle control to boost power from a single 1V cell.

The circuit of Figure 5 shows how to use the duty-cycled boost concept to solve the basic problem of powering a microcontroller-based system from a single coin-type alkaline battery cell. The circuit is similar to the circuit shown in Figure 3, but utilizes a very low voltage and very low supply current TS1001 op amp as a comparator, replacing the TSM9119. Also, the circuit has been simplified, as it provides lower currents.

The circuit operates from battery voltages as low as 1V, and provides power bursts at 1.8V, suitable for “burst powering” a microcontroller at its specified VDD=1.8V in short durations. During the “off-time,” the circuit provides the microcontroller a standby voltage of at least 0.9V, specified in microcontroller spec sheets as the “RAM retention voltage.”Alternatively, the load (microcontroller) may be disconnected entirely with the optional load cutoff circuitry, if desired, ensuring the microcontroller is completely off with zero leakage.

There is no fixed on-time with this circuit; instead a DONE control input is added. The microcontroller, when done with its operations, pulls the DONE line high, effectively “cutting the power cord” and shutting down the burst by resetting capacitor C1 (note that Q2's collector and emitter are reversed to ensure a low Vcesat for headroom reasons). The charge pump in this circuit is directly driven by op amp U1's output, which supports the 350μA burst currents. If higher currents are needed, the circuit may be modified with the additional circuitry of Figure 3.

Figure 6

'On-time' waveforms for the circuit in Figure 5.

“On-time” waveforms for the circuit in Figure 5.

In summary, employing a low-power, analog, duty-cycling clock, operating as an “always on” timer consuming around 500nA, can be a useful approach for ultra-low-power systems, cutting system power by cycling circuitry on with a very low duty cycle, providing boost capability without a regulator, and even burst powering a microcontroller.

Footnote:
1. Troubleshooting Analog Circuits by Bob Pease, page 66.

3 comments on “Applying Duty-Cycle Control to Save Power

  1. Brad Albing
    February 26, 2013

    Martin – this is a very clever idea.Never thought of making an extremely low power timer like this to periodically wake up the other parts of the system. Previously when I've considered any sort of timer, I've gotten stuck in thinking about this the same old way. I would assume that it must be very accurate, so that meant a real-time clock (RTC) – which of course draws more power. And all for accuracy that's not really needed. So thanks for forcing me to rethink.

  2. Brad Albing
    March 24, 2013

    By the way, how often have you seen this sort of a timer used in a design? I.e., are there any actual applications with which you are familiar? (Not asking for a list of companies doing this – don't want to give away secret company information.)

  3. Brad Albing
    March 27, 2013

    Martin – I'm looking forward to more ideas from you along these lines. Keep 'em coming.

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