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Keith Sabine
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Automating Analog Layout
Keith Sabine  
5/8/2019   Post a comment
There has been vast progress over the last 30 years or so in digital layout automation, which has made it possible to develop complex digital ICs relatively quickly. However, for analog layout, techniques are still much the same as they were years ago.
Electrically Correct Analog Layout
Keith Sabine  
3/17/2017   1 comment
Constraint-driven Analog Placement and Routing
Keith Sabine  
10/19/2015   Post a comment
Although digital design productivity has improved massively since the introduction of synthesis, advanced place and route and timing-driven design, analog design still relies on circuit simulation, manual layout and verification.
Using Deep N Wells in Analog Design
Keith Sabine  
5/7/2015   2 comments
On a conventional CMOS process, NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply
Latchup and its prevention in CMOS
Keith Sabine  
1/14/2015   5 comments
Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.
Layout-Dependent Effects in Analog Design
Keith Sabine  
10/9/2014   8 comments
Analog designers have always had to worry about physical layout to get good matching of devices.
Power Routing in Analog Design
Keith Sabine  
9/2/2014   7 comments
Widths of power tracks need to be considered carefully for analog layout.
Improving Analog Design Time
Keith Sabine  
7/9/2014   10 comments
Designers can estimate parasitics early in the design flow, at the RTL level, to see if they meet timing and power criteria. Thus design changes can be iterated relatively quickly until the design goals are met, with detailed layout following.
Matching in Analog Layout
Keith Sabine  
5/20/2014   Post a comment
Analog circuits often use structures like differential pairs and current mirrors, where matching of device characteristics such as the threshold voltage Vt is important.
Is It Time for Custom Design Tools to Catch Up With Digital?
Keith Sabine  
4/18/2014   5 comments
Over time in the semiconductor industry, several technology shifts have required EDA tool vendors to develop new solutions. We are once again at such a shifting point in the traditional methods of design.
Analog Layout Automation: An Unsolved Problem
Keith Sabine  
7/9/2013   4 comments
Better tools are needed to do layout of analog ICs. Using tools designed for digital devices will continue to take too long and produce unsatisfactory results.




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