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Content posted in June 1999
Board design toes transmission line
6/8/1999   Post a comment
As CMOS semiconductor density advances, ICs are getting faster while the number of high-speed nets multiplies. Interconnects at the board and system level have become the limiting factor to increased system performance and EMI compliance. Every engineer working on high-performance systems has an EMI or signal-integrity horror story, rooted in limited engineering insight. The challenges of designing high-performance systems will not diminish. Waiting to debug a product until after prototype fabri
Characterization key in analog IP
6/8/1999   Post a comment
Analog intellectual-property design verification, characterization and behavioral model generation are extremely engineering- and computer-intensive processes. Analog IP lies dormant because it is extremely difficult to reuse in its current form; changes in fabrication processes, loss of the original designer's intent and changing design performance requirements all create obstacles. Additionally, a lack of understanding of the range of performance often makes it easier to start a new design rat
Behavioral modeling tackles details
6/8/1999   Post a comment
Even with the intense activity in the development of such mixed-signal hardware-description languages as Verilog-AMS and VHDL-AMS, behavioral modeling is neither a new nor a difficult concept. The behavioral description of an analog or mixed-signal system is closely coupled with top-down design methodology. That modeling technology, through analog behavioral language, provides a base for design specification and documentation. A direct benefit is improved design efficiency, which better delivers
The art of automating analog design
6/8/1999   Post a comment
To presage the annual Design Automation Conference (DAC) in New Orleans June 21 to 25, this week's Signals section homes in on design tools for analog and mixed-signal electronic systems, where the designs flows are significantly longer and more difficult than those for digital logic. An oft-repeated maxim is that while analog will take up less than 20 percent of the circuit area of a new IC or system, the design effort required can easily consume 80 percent of allocated time.

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