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Content posted in August 2001
Phase- and Delay-Locked Loop Clock Control in Digital Systems
8/17/2001   Post a comment
High-speed chips require low-skew clock distribution that can handle high clock rates and sophisticated features such as programmable duty cycle and delay. Zeljko Zilic of McGill University discusses frequency synthesis along with the critical phase- and delay-locked loop (PLL and DLL) circuit designs needed to meet chip-speed criteria.
Analog Circuit Design Using Genetic Algorithms
8/13/2001   1 comment
Genetic algorithms (GAs) offer some impressive advantages for analog-circuit optimization. Kenneth Noren and John Ross discuss how to apply such algorithms for adjusting circuit parameters and describe a number of circuits designed with GAs.
Cracking the Analog-Design Nut
8/8/2001   Post a comment
SoC designers face a difficult problem in incorporating analog and mixed-signal blocks into their mostly digital chips. However, new breeds of synthesis and physical-implementation EDA tools are helping these designers in Cracking the Analog-Design Nut.
Designing Operational Amplifier Oscillator Circuits for Precision Resistive and Capacitive Sensor Applications
8/3/2001   Post a comment
The design of RC operational amplifier oscillators requires the use of a formal design procedure. ON Semiconductor's Jim Lepkowski describes a design procedure for two-state variable oscillator circuits you can use in precision capacitive-sensor applications.

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