“Ultra-Broadband” is defined as any product with more than 5 octaves of 3dB bandwidth. Products with this level of bandwidth are useful for applications, such as laboratory instrumentation, fiber optics, UWB (Ultra-Wide Band) transmission, radar, jammers, and military frequency-hopping radios. No matter how you design them, designing ultra-broadband amplifiers is a challenge from technology to topology.
When selecting a technology, chasing the highest fT is not always the best solution. As we know, some SiGe or CMOS transistors offer 200GHz peak fT , but only at select low-voltage (i.e., low-power) levels. Using FETs in InP and/or using very small gates below 0.1μ can also get high fT , but often at the expense of reliability. Therefore, most commercial, ultra-broadband amplifiers use a 0.15μ power PHEMT process. It demonstrates the best compromise of power density and fT as shown in Figure 1. It also has proven reliability.
Figure 1. Typical fT (GHz) of a 0.15μ PHEMT FET (150μ) over gate and drain voltage
Within our day-to-day designs, engineers strive for the least amount of series inductance (bond wires and transmission lines) and shunt capacitance (small gates and transistors). But there is no way to totally remove all parasitic series inductance and shunt capacitance that eventually degrades high-frequency performance.
To move above the parasitic limits that plague a broadband design, one must incorporate them into the design. This is commonly done by creating an artificial transmission line around the parasitic. Figure 2 shows a classic transmission line. Typically the shunt capacitance is the dominant parasitic in an amplifier, so series inductance is added to create an artificial transmission line. The only limit to this technique is the cut-off frequency: f = 1/[π√(LC)]
The distributed (or traveling wave) amplifier is built upon the artificial transmission line technique. In this amplifier, the shunt gate capacitance is spread out, stage-to-stage, with a reactive inductance in between. This builds an artificial transmission line, as demonstrated, where the shunt R and C are the gate input and the series L are printed MMIC transmission lines.
In reality, there are two transmission lines: one on the gate and one on the drain side. This is best shown in Figure 3.
I believe that when using the theoretical techniques shown above, some very practical amplifiers can be built. Let's look at one such device on the next page.
Here a cascade arrangement is used to provide the best isolation and control. Arranged in seven sections, they can be cascaded into a DC to 67GHz amplifier as shown in Figure 4 and measured in Figure 5.
Even more practical, the technique of incorporating parasitic elements can be applied to a packaged, surface mount plastic part. Engineers within our industry have integrated not only the package, but the bias tee, blocking capacitors and bypassing into an active amplifying transmission line. This is an excellent example of how to incorporate parasitics into the design early, so as to move above the parasitic limits that could potentially make the board design less efficient.
How are you building your designs today? Are you including parasitics early in the design process? Or are you achieving high-broadband performance using other innovative techniques? Please share your ideas.
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This type technique might be used to save battery, as charging battery by using parasitic current. This might require a more study to understand parasitic behavior in the circuit. This blog reminds us for parasitic current application in the circuit.
Considering the requirements of modern integrated circuit design such as low cost, low power consumption, and high integration level, CMOS offer great potential for most broadband design.
i agree we sometimes take advantage of parasitic effects to achieve a function in a component and best condition known to us is latchup.
A circulated terminator for ending a transmission line joining a plurality of IC. The terminator includes a plurality of a capacitor and resistors that is typically an ESD structure.