My last two blog posts have described where you can find analog technology in unusual places at the 2014 International Solid State Circuits Conference, which starts Sunday, Feb. 9. If your interest is less in applications of analog technology than other problems, and you want to find out what’s happening in real analog, here’s where you should be.
Let's start at Sessions 11 (Data Converter Techniques) and 17 (Analog Techniques), back-to-back programs scheduled for Tuesday, Feb. 11.
The data converter session will cover a variety of very impressive achievements in low power converters, such as a 10-bit A/D converter consuming just 0.6 nW. Many of the converters this year combine multiple techniques, such as oversampling successive approximation, subranging successive approximation, and SAR-assisted pipeline.
The 11 papers in the analog techniques session cover audio amplifiers at both ends of the power range: an integrated 80V 45W Class-D power amplifier and a 0.9V 6.3μW multistage amplifier driving 500pF capacitive load. Since most experienced analog engineers know that many amplifiers spend some time as oscillators, there are two fascinating oscillator papers, both for real-time clock applications, usually based on a 32kHz crystal.
A paper from Mediatek describes a 1.89nW/0.15V self-charged crystal oscillator. A paper from TI describes a high-power but apparently more stable and accurate circuit — a 33kHz RC oscillator with ±0.21% temperature stability and 4ppm long-term stability consuming 190 nW. That's 100x the power of the previous paper, but 190 nanowatts is still pretty low.
Session 21 (Frequency Generation Techniques) will include several papers on various flavors of PLLs. The standout papers, in my opinion, cover a 60GHz PLL in 40nm CMOS that burns only 42 mW and a 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS.
Session 22 (High–Speed Data Converters) will take place at the same time as Session 21. The minimum table stakes in this session is a conversion rate of 1 Gs/s. It's hard to compare converters with different resolutions and conversion rates, but if we compute a figure of merit for each one, using the number of quantization levels (2^N) times the sampling rate, we get a number we can use for comparison. The first paper covers a 90Gs/s eight-bit A/D converter presented by IBM Switzerland and EPFL. It runs away with the highest value, but it consumes 667 mW of power. If we divide the quanta-times-sample-rate number by power consumption, then the lead goes to the device in an MIT paper (10 bits at 1 Gs/s for 18.9 mW).
There are two other places for analoggers to experience the most of the ISSCC.
On Sunday, Feb. 9, there will be an all-day forum session, “Digitally Assisted Analog and Analog-Assisted Digital in High-Performance Scaled CMOS Process,” where you may pick up some new tricks.
But you can't stay for the entire session. You have to get to David's Restaurant in Santa Clara, Calif., by 5:00 p.m. Though it is not an official ISSCC event, there will be a gathering of analog aficionados hosted by Paul Rako. Go to his website and sign up, so there will be a badge ready for you. This party began more than 20 years ago, when Jim Williams hosted it. Many of the analog world's top guns will be there swapping stories and sharing experiences.