At ISSCC, IMEC details ADC, 60-GHz wireless developments

SAN FRANCISCO — At the International Solid State Circuit Conference (ISSCC) here, IMEC researchers detailed their latest feats in data conversion and wireless 60 GHz.

On the data converter front, three papers detailed ultra-low-power analog-to-digital (ADC) converters targeting wireless software-defined radio (SDR), 60-GHz communication and sensor networks applications. IMEC, the Leuven, Belgium, research consortium, has submitted patents for the architecture of its SAR (successive approximation), Flash and CABS (comparator-based asynchronous binary-search) ADC families, hoping to make these available for product development through licensing as white box IP.

IMEC researchers developed a two-step, 7-bit 150-Msamples/s ADC with a record figure of merit of 10 femtoJoules per conversion step. The innovative CABS ADC architecture consists of a 1-bit coarse ADC and digital-to-analog converter followed by a 6-bit sub-ADC. The 6-bit sub-converter consists of a self-clocked (asynchronous) binary tree of comparators with embedded threshold. The input signal is applied in parallel to all comparators, as in the case of flash converters, but only 6 comparators are triggered by the binary search conversion. The power consumption scales linearly with the sampling rate and equals 0.89 microW per MHz clock rate, resulting in a record figure of merit of 10 fJ/conversion step. “This is a factor 22 improvement compared with state-of-the-art ADCs with a similar number of bits and sampling speed,” said Rudy Lauwereines, vice president, Nomadic Embedded Systems, at IMEC. The ADC was fabricated in 90-nm digital CMOS, and occupies less than 250x250microm 2 .

Meanwhile, in a second paper, IMEC researchers reported beating IMEC's own record SAR ADC with improved power efficiency, making it noise-robust. IMEC realized a 9-bit 40-MSamples/s fully-dynamic noise-tolerant SAR ADC achieving a record figure of merit of 54 fJ/conversion step. “This figure of merit is a 16 percent improvement compared with IMEC's record design presented at last year's ISSCC,” said Lauwereines. That ADC was the world-first charge-based SAR ADC that uses charge-domain signal processing to overcome the fundamental power bottlenecks in successive approximation ADCs. The new design is optimized with an improved sample-and-hold and a noise-robust approach by leveraging redundancy in the search algorithm.

And in its flash ADC, IMEC researchers reached sampling speed above 500 Msamples/s, with a record figure of merit of 50 fJ per conversion step. This is three times better compared with the best ever reported converters with sampling speeds over 500 Msamples/s.

In another slew of technical papers, IMEC researchers introduced a prototype of a 60-GHz multiple antenna receiver. The consortium is inviting the industry to join its 60-GHz research program. The 60-GHz band offers massive available bandwidth that enables very high bit rates of several Gb/s at distances up to 10 meters (about 33 feet). IMEC built its rf solution in a standard digital CMOS process.

The prototype implements a unique programmable phase shift of various incoming signals, which is necessary for beam-forming. The device contains two antenna paths, each consisting of a low-noise amplifier and a down-conversion mixer. The programmable phase shift is realized on the same chip. It starts from the signals of an on-chip quadrature voltage-controlled oscillator (QVCO). This QVCO design reportedly combines the highest oscillation frequency with the largest tuning range ever reported in CMOS.

“This multiple antenna receiver is the first step towards a complete CMOS-based phased array transceiver for 60-GHz wireless personal area networks,” said Lauwereines. “In the next phase of development, we plan to implement four antenna paths using 45-nm CMOS technology and to integrate other subsystems, such as the phase-lock loop, analog-to-digital converter and the patch-antenna array itself.”

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