(Note: This article originally appeared on EE Times Europe's Analog site. )
A new triple-rate (3G/HD/SD) audio/video clock generator from National Semiconductor Corp., eliminates the need for external clock conditioning in professional and broadcast video equipment.
The LMH1983 produces all the major video and audio reference clocks required for a broad range of applications. The highly integrated LMH1983 also provides the industry’s lowest-output jitter (40 ps peak-to-peak), enabling Society of Motion Picture and Television Engineers (SMPTE) compliance using field-programmable gate array (FPGA) SerDes transceivers.
The LMH1983 replaces three external phase-lock loops (PLLs), voltage-controlled crystal oscillators (VCXOs) and loop filters to simplify design, reduce bill of materials (BOM) cost and conserve board area. It generates four simultaneous low-voltage differential signaling (LVDS) clocks with dedicated top-of-frame timing pulses, providing a “plug-and-play” solution with minimal FPGA programming.
The LMH1983 also eliminates the time-consuming PLL tweaking, required with discrete A/V clock generator implementations, accelerating time to market. The LMH1983 supports SMPTE serial digital interface (SDI) video and digital audio AES3/EBU standards for 1080p high-definition (HD) video cameras and video capture, conversion, processing, editing and distribution equipment.
For video processing and format converter cards, the LMH1983 simultaneously provides the SMPTE 424M system clocks (148.5 MHz and 148.5/1.001 MHz) required by the latest generation of FPGAs. For broadcast studios that “genlock” video equipment, the LMH1983 generates a synchronized high-frequency clock at the digital pixel rate phase-locked to the horizontal and vertical timing signals of the reference video signal. For applications that embed the audio signal or remove it from the video signal, the LMH1983 generates synchronous audio and video clocks locked to the video reference signal.
Offered in a 40-pin LLP package, the LMH1983’s dual-stage PLL architecture integrates four PLLs with three on-chip voltage controlled oscillators (VCOs). It creates simultaneous SD video, HD video (2x) and audio clocks from any of the following compatible references: H/V sync from National’s LMH1981 video sync separator outputs, recovered H/V syncs from an SDI stream or a 27 MHz clock source. The LMH1983 features automatic input format detection, digital frequency holdover on loss of reference and simple programming of multiple A/V output formats, as well as genlock or digital free-run modes.
The LMH1983 recognizes HVF syncs for the major video standards and 27 MHz, 10 MHz and 32/44.1/48/96 kHz audio word clocks. It includes an I2C compatible bus interface for programming device registers and reading device status. The LMH1983 operates from a 3.3 V supply and features power efficient operation. Each PLL can be independently powered on/off to conserve system power.
Availability and Pricing
Available now, the LMH1983 is priced at 16 US Dollar each in 1,000-unit quantities.
Related link: LMH1983