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Dennis Feucht

Neuronics Creates Highly Efficient Memory, Part 2

Dennis Feucht
D Feucht
D Feucht
11/7/2013 4:50:37 PM
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Blogger
Re: Holographic memory
You pose a most pertinent question. First, I should note that Albus's scheme is not analog at all; in my reading of his work (and speaking to him), all of it has been implemented on digital computers.

To select which addresses should be read (and added) for a given input, Albus and his group used hash coding, but I do not recall the hash algorithm as being given. It is certainly a factor that needs significant consideration. As I recall, Albus's implementations tried to randomize the hashing as much as possible - that is, be as random in selection of addresses as possible.

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rfindley
rfindley
11/6/2013 4:55:24 PM
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Newbie
Holographic memory
@Dennis, This is essentially holographic memory.  I use a vaguely similar method in my neural network work.  It is very effective for memory compression.

I assume the "address decoder" is a fixed function in CMAC?  I'm curious if/how related or similar data is grouped for maximum compressibility with minimal loss of data quality.

 

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samicksha
samicksha
11/5/2013 2:30:11 AM
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Artist
Re: Neural Network based memory accessing
This sounds interesting and somewhat new to me, curious to learn more on same, can we relate this to the amount of information which can be stored in the network and to the notion of complexity.

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DaeJ
DaeJ
11/3/2013 6:05:44 PM
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Master
Re: Neural Network based memory accessing
I really consider the memory reading access time as part of memory cycles in the computer architecture. This method requires the extra cycles to calculate the summation. But extra cycle causes delay for other instruction. Also, memory reading would be checked to avoid reading error, which is requiring other cycles to meet address and data bus timing requirement.

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Netcrawl
Netcrawl
11/3/2013 8:49:25 AM
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Master
Re: Neural Network based memory accessing
@Dennis that was great! interesting one, communication delay (the delay between the processor and main memory) is the bottelneck of most system performance, complex memory hierarchies are require to handle this one,

In modern CMPs several processors cores are accessing the same shared memory resources simultaneously, this is where the problem start, that why we need something new capable of everything-a well-designed memory systems should be used to optimize the speed and access efficiency of shared memory resources. 

@Daej I heard that one, its fascinating and quite interesting, But I think they no longer interested on that, Google already owned Motorola, so we expect Google to change Motorola's focus.   

 

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DaeJ
DaeJ
11/2/2013 5:11:52 PM
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Master
Neural Network based memory accessing
It sounds like memory access is based on weight of each node similar to Neural Network. Long time ago, Motorola engineer implemented analog circuit of neural network.  I concern a little bit about the calculation time of summation to access the contents of memory by address.

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