One useful dynamic application of μCs is as analog-to-digital converters (ADCs). ADCs over the years have gone from complete DVMs as instruments to embedded subsystems, to a few components. This two-part article presents some minimalist techniques for implementing μC-based ADCs.
Minimalist A/D Conversion
Multiple schemes have been devised over the years for A/D conversion. Some are simple, not very fast, and not very precise, such as the single ramp converter, as shown below; charge a capacitor with a current source, thereby generating a ramp.
When the ramp crosses the unknown voltage, vx, to be measured, the time interval from the start of the ramp to vx, as detected by the comparator, is measured. For a (linear) ramp, the time is proportional to vx. A counter is reset (or overflows) at the start of the ramp and counts an accurate clock, such as a prescaled crystal-controlled μC clock. The ramp voltage is reset by a single transistor.
This ADC is easily implemented using a μC, and requires one counter, an input-port bit from the comparator and an output-port bit to reset the ramp. The ramp ADC is subject to inaccuracy because ramp slope variation can be caused by the ramp current source, capacitor drift, and comparator input-voltage offset and bias-current errors. It is conceptually simple, but we can do far better than this with fewer components.
Another category of ADCs are the parallel-feedback types. They use a DAC and comparator to set bits of the converted measurement. The general scheme is shown below.
Depending on the logic, the converter can be one of multiple types. The successive-approximation scheme is predominant because it converts one bit per iteration, which takes n cycles to convert n bits independent of the converted value of vx. This scheme is well-suited for μC-based A/D conversion.
μC-Based Parallel-Feedback ADCs
The parallel-feedback converter can be adapted to most μCs as shown below.
The μC performs the logic. For the simplest and least desirable ADC, the ramp converter, the μC logic is given in algorithmic form below:
0. Ramp ADC
1. Set OUT to zero: OUT
2. Input the IN bit.
3. If IN = 0, then VX
OUT; go to 1.
Else increment OUT: OUT
OUT + 1.
4. Output OUT; go to 2.
The second ADC option, also differing from the others in its logic, is the tracking ADC. The advantage of the tracking converter is that it follows the analog waveform, though it is subject to digital slew-rate limitations for fast changes in vx. The tracking algorithm is given below.
0. Tracking ADC
1. Output OUT.
2. Input IN.
3. If IN = 0, then decrement OUT: OUT
OUT – 1.
Else, increment OUT: OUT
OUT + 1.
4. Set VX to OUT: VX
5. Go to 1.
This algorithm is not more complicated than that of the ramp converter but has the real-time tracking advantage. If the input waveform changes too quickly, the tracking ADC has the disadvantage that its DAC output slews, taking multiple iterations to “catch up” with the waveform and once again track it accurately.
The successive-approximation (SA) ADC uses the SA algorithm which is somewhat more involved but has the advantage of constant, input-independent conversion time. It uses two memory locations labeled SAR and SR. C is the processor carry bit.
0. Successive-Approximation ADC
1. Clear SR and SAR: SR ← 0; SAR ← 0.
Set C to one: C ← 1.
2. Rotate SR right, with C.
3. If C = 1, then return with VX ← SAR.
4. Output SR OR SAR to OUT: OUT ← SR OR SAR.
5. Input from IN.
6. If IN = 1, then go to 2.
7. Else, set SAR to SAR AND /SR: SAR ← SAR AND (NOT SR).
(Alternative: SAR SAR AND (SR EOR 1111...).
8. Go to 2.
The 1 bit, initially in C, is rotated (closed-loop shifted) right, into SR, one bit per iteration. When it returns to C (step 3 checks this), the procedure is finished. Step 4 sets the SR 1 bit in the SAR. If the comparator (IN) is high, vx is still greater than the SAR value, and this test bit remains set. If IN is low, the set bit made SAR too large, and it is cleared in step 7. Each bit, beginning with the MSB, is tested and then left set or cleared in SAR. Step 7 can use the clear-bit command for μCs that have it, with SR as the mask.