In the second part of this series, Build Your Own Curve Tracer, Part 2: TPA202 Circuit Description, the TPA202 input-port and display-logic circuits were described. This article continues a summary of the circuit description, derived from the TPA202 Manual which is open-source, available from innovatia.com and contains more detail.
The circuit diagram of the output-port SMU is shown below. (See the first article of this series. Build Your Own Curve Tracer, Part 1: Introduction, for TPA abbreviations.)
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The output-port SMU is more involved than that of the input port because it has a larger output-voltage range and can dissipate more power. To minimize thermal design, power dissipation is minimized by using a segmented-amplifier output stage. This kind of power-reducing scheme is familiar in audio, but what is different is that the segmentation is a parallel instead of a series scheme. By minor design rescaling of transistor voltage ratings and some resistors such as R61 and R63, the supply voltages can be increased significantly.
The output drive (ODR) amplifier has a ten-turn front-panel pot input that adjusts the magnitude (not polarity) of the output voltage. Its output is 0 V zero-scale (zs) to +4 V fs. The amplifier has its own floating supplies of +12 V(F), +20 V(F) and +40 V(F). Like the input-port amplifier, it has an op-amp first stage, but then has a complementary-cascode second stage with emitter-follower buffer, and a Darlington output stage. Because of the wide output voltage range, the output stage is a segmented amplifier. Q21, Q22 form a comparator that switches the active output stage between Q15 for the low-voltage range and Q16. With two supplies, neither output emitter-follower conducts the fs current of 0.1 A with more than about 20 V across it, thereby limiting its maximum power dissipation to about 1 W. The output has overcurrent protection of R51, Q14. At somewhat over 100 mA, Q14 conducts and pulls the translator-stage output voltage across load resistor R56 to the amplifier output node voltage.
The translator stage output is buffered by common-collector (CC) BJT, Q20. The voltage translator has a common-base (CB) NPN input, Q18, followed by the CB PNP stage of Q19. The circuit allows the high-voltage node at the bottom of R55 to be limited only by the breakdown voltages of Q19, Q20. The cascode input and output voltages, however, are (nearly) the same, near floating (F) ground. The Q19 base circuit biases Q19 at VBE = 0.84 V plus a diode drop below the +40 V supply. D22 is approximate compensation and tracking for the Q19 b-e junction, to keep the voltage across R55 a constant 0.86 V so that it sources a constant 1.7 mA of current.
When the op-amp output increases, the voltage across R52 decreases and Q18 current decreases. This leaves more of the 1.7 mA from R55 to flow through Q19, dropping increased voltage across R56, and the output voltage buffered by Q20 increases. This stage has no polarity reversal. Neither does the Darlington output stage. R50, R49 form a feedback divider so that the entire OUT amplifier is noninverting.
The additional op-amp in the dual package is put to use in the floating-supply system of circuitry by driving an LED which lights in proportion to the output voltage magnitude. This offers the user an immediate visual indication of the magnitude of the output voltage, and as OVDR is adjusted, the LED can be seen to glow brighter or dimmer, giving the front-panel operator analog visual feedback. On TPA202 design variations with dangerously high output voltages, this LED also functions as a warning light. This LED could be mounted in the DUT test fixture or included on the front-panel.
The bipolar output of the OUT SMU is achieved by swapping the output terminals of its amplifier using a DPDT (2P2T) switch, S5. An output-polarity-switched amplifier must have a floating ground because when it outputs negative values, its own ground is the + port terminal and its output is the port terminal, which connects (through the OISN circuit) to the INP SMU and COM ground. Therefore, the OUT SMU supplies are isolated from the other supplies and float with respect to ground. They float because they are connected through ISN circuitry and the polarity switch to the ground of the rest of the instrument and thus are not isolated from it. However, the supplies must not have any appreciable spurious conductive paths to the grounded system because that current will find its way back to the floating supply through current sense circuitry, causing measurement error.
The high voltage range of the ODR is outside the input range of op-amps powered by the low-voltage supplies and does not allow for simple circuit design of a OISN circuit as for the IISN. Instead, the OISN is made low-side and is between the port terminal and the amplifier terminal, on the output side of the polarity switch. As in the INP port, the amplifier output voltage is not the port voltage because of the series ISN resistor sense-voltage drop. The OISN has the same switched sense-resistor scheme as the IISN, followed by a ×10 amplifier (U11), though it is not the 2-op-amp diff-amp of the IISN. The CM range is essentially zero for low-side ISNs.
U11B is a ×1 voltage buffer of the OVDR-ISN node, the amplifier output side of the ISN (after the polarity switch). The common side of the sense resistors returns to the port terminal which is the COM node. U11A is an inverting op-amp that amplifies the sense-resistor voltage by ×(10) from the VS node, the output of U11B. This voltage is actually νS because positive port current will flow from the COM ground to the left through the sense resistors (R43, R44, R66 - R69, R75, R76). The inversion of U11A presents the correct polarity of voltage at OISN. The + input of U11A references the OISN output to COM ground, the same as the DVM ground. This U11A diff-amp has essentially no common-mode input voltage because of low-side current sensing, and has no CMR adjustment. However, op-amp input voltage offset can cause measurement error, and a lower-VIOS op-amp than a TLV2372 or commodity-grade LF353 was chosen - the TL2272A. The slower, higher-gain TLC2262A with similar VIOS is an alternative. The better op-amps eliminate yet another trimpot and their extra cost is less than an adjustment - another advantage of newer op-amps.
U12 supplies OVSN to the DVM and includes voltage sense (VSN) compensation, to subtract the effect of νS in series with the port output voltage, vO. The problem is demonstrated in the drawing below.
To recover the output-port voltage, νO (shown diagonally in the diagram with + sign at OVDR+ and sign at ground), a voltage divider (R87 and R89 || R85) scales down νO to within the range of the circuits operating on ±5 V supplies. The divider causes a complication: its divider current. To avoid having the divider current flow through ISN (RS) and cause OISN error, the bottom end of R89, R85 is returned directly to the output of the floating amplifier, OVDR-ISN, instead of ground. However, the voltage across the OUT-port, νO, is to ground, not OVDR-ISN, and the divider has across it νO νS. Consequently, the + input to U12B is the superposition of these two voltages as they are divided in opposite directions through the divider. The division ratio from OVDR+ as input is
where the divider attenuation is
The goal is to make the measured OVSN = T x νO. Consequently, (1 T) x νS is an error voltage at the output of U12B. To subtract it from OVSN, add (1 T) x νS to the U12B output. The path through U11B, U12A supplies 2 x (1 T) x νS, and the divide-by-2 R88, R95 reduces it to (1 T) x νS. Then to correctly scale νO, the R87, R89 || R85 divider divides by half the required amount, and the 2 remainder is divided by R88, R95. Then OVSN is a function of νO and not νS.
In the next part, we continue with the remaining DVM and power-supply blocks of the TPA202.