The x1 voltage amplifier or “buffer” is a standard building block of analog design. This article presents the design of a discrete, low-parts-count, high-performance, matched-transistor buffer, and covers some of the finer points in optimizing its design.
In an era when a buffer is most easily implemented with an op-amp, why use a discrete circuit? When high precision and minimal space are not worth the extra cost, a dual-JFET amplifier costing 50 cents in parts, can deliver multiple hundreds of megahertz of bandwidth with an offset error of 10 mV or less and an offset drift of 10 μV/oC or less. By applying ingenuity, good performance can be attained with discrete-component circuits, which will still be available when the op-amp is obsolete. The buffer can become part of your design library.
Buffer Amplifier Circuit
The design goal of the 1 voltage amplifier is to achieve the ideal voltage amplifier: infinite input impedance, zero output impedance, and linearity. To achieve high input impedance, a JFET instead of a BJT is used, as shown in the buffer circuit below.
Discrete JFETs are available from over a half-dozen suppliers, including:
For low cost, discrete JFETs are chosen, despite the advantages in thermal tracking of dual devices in a single package, such as the 2N3958, 2N5196 through 2N5199, and the 2N5564 through 2N5566. These dual parts tend to cost anywhere from $4.50 each to over $40 for the best ones. If you can absorb the additional cost, these are superior than discrete JFETs in their thermal tracking.
Some discrete n-channel JFET alternatives for the buffer are the 2N5484 through 2N5486. The 2N5485 costs about $0.20 each (in hundreds). It has a drain current selected for a nominal design value at midrange of IDSS = 7 mA (IDSS is ID @ VGS = 0 V) in a 4 to 10 mA specified range. Furthermore, the two JFETs are chosen to match using a curve tracer. This takes less than one minute per pair, by sorting them into matching IDSS bins, for an additional $0.10 of U.S. labor.
Next, choose some standard supply voltages: VDD = +12 V and VSS = –5 V. These supply voltages are common in both desktop computers and instrumentation.
The first design feature of matched JFETs is the static (dc) tracking of the matched transistors. If the gate of the lower transistor, QL, is connected to its source, then VGS = 0 V, and the drain current will be IDSS. If this same current flows (with open load) through QU, then because it is matched, its VGS is also zero and there is no voltage offset from input to output.
This nifty technique can be improved by setting the JFET operating point to the zero TC point instead, where thermal drift of VGS with a given ID is minimal over temperature. For JFETs, the zero-drift VGS is about 0.8 V above the pinch-off voltage. The value of this VGSZ is where the ID lines for various temperatures intersect. For the 2N5485 this is at about -1.2 V. And this is about 0.8 V higher in value than the pinch-off voltage of around -2 V. The curves for the 2N5485 (Siliconix) are shown below.
Using these values, Rsl = Rsu= Rs= 1.2 V/5 mA = 240
, a 5 % value. The voltage drop across Rsl is compensated in the waveform path by a similar drop across the matched resistor, Rsu. For better matching, these resistors can be 1 % tolerance instead.
With a varying input voltage, the power dissipation of the two JFETs will also vary. A change in power causes a change in silicon temperature, which results in thermally-induced electrical noise, or “thermals,” in the amplifier response. This “noise” is waveform-related and can better be regarded as thermal distortion. It can be minimized by setting the operating-point (op-pt or bias) for maximum power dissipation in the JFETs with no varying input (that is, at the op-pt). The change in power (which we want to minimize) is least around the peak power value where the derivative magnitude or slope of the parabola is least.
Let the operating-point - the static bias current - of the JFETs be I0. Then the power dissipated by upper and lower transistors is
where vL is the load voltage (across RL). The difference in power dissipation is
The power graphs are shown below, plotted using MathCAD.
pD, the change in power with vL is minimum, which is desired to minimize thermals. Differential power is maximum at
Another voltage of passing interest is where pu and pl are equal. Solving for vL at
pD = 0 W,
On the above plot, vL0 = 5.3 V. Though the power dissipation is matched at this output voltage, any change around this value causes a larger change in Δ
pD than the same change in vL around vL (max). Consequently, the preferred bias point is at vL (max).
On the plot, vL (max) = 1.62 V. However, the given circuit parameters result in a static vL of 0 V instead. To adjust the static voltages across the JFETs, an additional series resistor, Rc is added. For the general case, let the static output voltage be VL. Then to set the vertex of the differential-power parabola at VL,
and solve for the value of VDD that will satisfy the desired condition:
Then substitute VL and the supply VDD into
For this design, Rc = 490 Ω. Cc bypasses Rc so that no appreciable voltage variation occurs at the drain.
Matched-BJT Buffer Amplifier
JFETs are superior to BJTs in that they have high input resistance and low input bias current. However, for the same temperature coefficient (TC), current matching must be a decade better for JFETs than BJTs. This is why the input offset specification of JFET-input op-amps is generally worse than their BJT counterparts. Put simply, BJTs match better than JFETs.
If your buffer design does not require high input resistance, use BJTs instead. The biasing will have to be done somewhat differently, using a fixed base voltage for QL. This makes QL a current source which drifts with temperature because of VBE(T). A matched QU drifts similarly with the same bias current, and dynamic emitter resistance,
is kept constant over temperature as ICL (= IEU) varies with temperature. As temperature increases, VBEL decreases and ICL increases. At the same time, reU increases with thermal voltage, VT, but increased emitter current compensates by decreasing reU. The TC of current from QL compensates for changes in re , which affects the buffer voltage gain.
The rudimentary buffer stage presented here can be improved by following it with complementary BJT CC stages, where the b-e junctions of NPN and PNP cancel. Better yet, if a matching NPN is placed in series with QL source, it compensates for the succeeding NPN CC stage.
(The derivations of buffer design and thermal equations are found in the book, High-Performance Amplifiers by the author. See www.innovatia.com.)