This is a guest blog from Steve Netto, a mixed-signal designer.
Innovations in the consumer industry over the past decade have greatly impacted the way SoCs are designed and drastically reduced the design cycle time. Companies now vie with one another on a global front to be among the first to meet the shrinking time-to-market window. If the recent changes in the consumer industry are any indication, given the increasing investment in Internet of Things (IoT), as well as other consumer devices, the market for mixed-signal designs are set to grow over the next few years, and the designs will considerably increase in complexity.
The increase in design complexity emerges from the increased use of sensor and RF devices within the SoCs. Analog design is the proverbial black art. Integrating it with digital designs and verifying the mixed-signal design within a short design cycle are among the biggest challenges to overcome in order to meet the market window.
Mixed-signal design environments are not entirely new. From an analog designer's perspective, engineers have been doing mixed-signal design for years. However, neither analog nor digital engineers are prepared to enter each other's domain of expertise. Analog engineers typically shy away from the complexity of SoC verification, while the digital engineers are uncomfortable with the fuzziness of analog design. Unfortunately, there is no way to avoid this interaction. SoCs are being designed with multiple feedback loops between the analog and digital domains, so it is impossible to verify the two domains independently.
One of the biggest challenges designers face while verifying a mixed-signal design is to manage the different versions and releases of the RTL design files, simulation vectors, PDKs, etc. In the following example, we will review some of the details of a mixed-signal design flow involving various verification paths.
Consider a sample design, which includes an analog spread spectrum PLL (SSPLL), along with a digital circuit providing the modulation of the signal. The general spectral distribution has to be measured on the modulated signal, and, as I mentioned earlier, verifying the analog design is typically beyond the scope of the digital design engineer. The spectral measurement in the mixed-signal simulation also needs to match the lab measurement from the test device, which has been fabricated using the digital circuit in an FPGA and the analog SSPLL on a test chip.
The basic design flow expressed above is shown in Figure 1.
Spread spectrum PLL mixed-signal design flow.
In this example, the SSPLL generates a base frequency of 480 MHz. Then the digital circuit provides a two-bit addition in the feedback loop in increments of 20 MHz up to 540 MHz. The modulation can be generated in a number of frequencies and shapes. In this example, we will look at the modulation of Sine 50 KHz, shown in Figure 2. The top signal is the two-bit digital signal generated by the spread spectrum digital block. The second signal is the analog signal generated by the SSPLL. The third signal is the frequency change of the SSPLL created by the two-bit digital signal. If we take a histogram spectral measurement of the third signal, we can see that it has the classic Batman distribution of frequencies, as shown in Figure 3.
Spread spectrum PLL modulated output Sine 50 KHz.
Spectral distribution of frequencies for the modulated SSPLL.
This spectral distribution from the mixed-signal simulation must match the measurement from the test device (which comprises the digital FPGA and the SSPLL test chip). In this case, a single set of SS digital RTL is written and the chip and FPGA versions are simply compiler options to create different interfaces.
Part 2 of this two-part blog will appear right after this part.